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Merged
Paebbels merged 21 commits into from
Jun 20, 2025
Merged

Add AXI4 Infrastructure Modules #18

Paebbels merged 21 commits into from
Jun 20, 2025

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@stefanunrein
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@stefanunrein stefanunrein commented Jun 11, 2025 •
edited by Paebbels
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New Features

  • New AXI4Lite components
    • AXI4Lite_Register
    • AXI4Lite_FIFO
    • AXI4Lite_FIFO_CDC
    • AXI4Lite_Termination_*
  • New AXI4 components
    • AXI4_to_AXI4Lite-Adapter
    • AXI4_FIFO
    • AXI4_FIFO_CDC
    • AXI4_Termination_*
  • New AXI4Stream components
    • AXI4Stream_FIFO
    • AXI4Stream_FIFO_CDC
    • AXI4Stream_FIFO_tempgot
    • AXI4Stream_FIFO_tempput
    • AXI4Stream_Stage
    • AXI4Stream_Mux (Arbiter)
    • AXI4Stream_DeMux
  • TerosHDL Project file
  • Added ocram_sdp_optimized
  • Added new RAM_TYPE for AMD/Xilinx UltraRAMs.

Changes

  • Renamed fifo_glue to fifo_stage.

Tests

  • AXI4Lite_Register

@Paebbels Paebbels self-requested a review June 19, 2025 20:40
@Paebbels Paebbels added the Enhancement Code improvements. label Jun 19, 2025
Paebbels
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Paebbels reviewed Jun 19, 2025
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Paebbels reviewed Jun 19, 2025
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src/bus/axi4/AXI4Lite/AXI4Lite_Termination_Master.vhdl
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@Paebbels Paebbels Jun 19, 2025

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rename 4x Terminations:

  • Master => Manager
  • Slave => Subordinate

Paebbels
Paebbels reviewed Jun 19, 2025
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Paebbels reviewed Jun 20, 2025
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tb/bus/axi4/AXI4Lite/AXI4Lite_Register/AXI4Lite_Register_TestHarness.vhdl Outdated
Comment on lines 181 to 182
S_AXI_ACLK => Clk,
S_AXI_ARESETN => nReset,
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@Paebbels Paebbels Jun 20, 2025

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Suggested change
S_AXI_ACLK => Clk,
S_AXI_ARESETN => nReset,
Clock => Clk,
Reset => not nReset,

@Paebbels Paebbels merged commit 881aa90 into VHDL:master Jun 20, 2025
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@Paebbels Paebbels added AXI4 AXI4 latest issue. See also AXI4-Lite and AXI4-Stream AXI4-Lite AXI4-Stream PoC.mem.ocram.* OnChip memory. Core: AXI4-Lite Register Testbench Testbench related. labels Nov 28, 2025
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@Paebbels Paebbels Paebbels left review comments

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@stefanunrein stefanunrein

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AXI4-Lite AXI4-Stream AXI4 AXI4 latest issue. See also AXI4-Lite and AXI4-Stream Core: AXI4-Lite Register Enhancement Code improvements. PoC.mem.ocram.* OnChip memory. Testbench Testbench related.

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@stefanunrein @Paebbels