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krishnamtibrewalakrishnamtibrewala
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[AIE2] Remove specialized instruction ADD_NC_GPR
1 parent 1d02ea4 commit 800ab8d

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9 files changed

+29
-36
lines changed

9 files changed

+29
-36
lines changed

‎llvm/lib/Target/AIE/AIE2GenInstrInfo.td

-4
Original file line numberDiff line numberDiff line change
@@ -24,10 +24,6 @@ let Itinerary = II_ADD_NC in {
2424
def ADD_NC : AIE2_mv_add_inst_mv<(outs OP_mMvSclDst:$dst), (ins eR:$s0, simm6:$imm), "add.nc", "$dst, $s0, $imm">;
2525
}
2626
}
27-
// II_ADD_NC_GPR was defined to avoid unnecessary resource dependencies when moving the result into a GPR
28-
let Itinerary = II_ADD_NC_GPR, isCodeGenOnly = 1 in {
29-
def ADD_NC_GPR : AIE2_mv_add_inst_mv< (outs OP_mMvSclDst_and_eR:$dst) , (ins eR:$s0 , simm6:$imm ), "add.nc", "$dst, $s0, $imm">;
30-
}
3127
let Itinerary = II_ABS in {
3228
let Defs = [srCarry] in
3329
def ABS : AIE2_alu_r_r_inst_alu<0b1000, (outs eR:$mRx), (ins eR:$mRx0), "abs", "$mRx, $mRx0">;

‎llvm/lib/Target/AIE/AIE2InstructionSelector.cpp

+2-3
Original file line numberDiff line numberDiff line change
@@ -793,9 +793,8 @@ bool AIE2InstructionSelector::selectStartLoop(MachineInstr &I,
793793
}
794794

795795
// Not a constant trip count, decrement at runtime
796-
auto ADDI =
797-
MIB.buildInstr(AIE2::ADD_NC_GPR, {I.getOperand(0)}, {I.getOperand(2)})
798-
.addImm(-1);
796+
auto ADDI = MIB.buildInstr(AIE2::ADD_NC, {I.getOperand(0)}, {I.getOperand(2)})
797+
.addImm(-1);
799798
I.eraseFromParent();
800799
return constrainSelectedInstRegOperands(*ADDI, TII, TRI, RBI);
801800
}

‎llvm/lib/Target/AIE/AIE2Schedule.td

-2
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,6 @@ def II_ADD_NC_DN : InstrItinClass;
156156
def II_ADD_NC_M : InstrItinClass;
157157
def II_ADD_NC_P : InstrItinClass;
158158
def II_ADD_NC_RS : InstrItinClass;
159-
def II_ADD_NC_GPR : InstrItinClass;
160159
def II_AND : InstrItinClass;
161160
def II_ASHL : InstrItinClass;
162161
def II_CLB : InstrItinClass;
@@ -448,7 +447,6 @@ InstrItinData<II_ADD_NC_DN, [SimpleCycle<DN_WM_PORT>], [1,1,1]>,
448447
InstrItinData<II_ADD_NC_M, [SimpleCycle<M_WM_PORT>], [1,1,1]>,
449448
InstrItinData<II_ADD_NC_P, [SimpleCycle<P_WM_PORT>], [1,1,1]>,
450449
InstrItinData<II_ADD_NC_RS, [SimpleCycle<RS_WM_PORT>], [1,1,1]>,
451-
InstrItinData<II_ADD_NC_GPR, [SimpleCycle<RS_WM_PORT>], [1,1,1]>,
452450
InstrItinData<II_AND, [InstrStage<1, [R_WX_PORT]>], [1,1,1,1]>,
453451
InstrItinData<II_ASHL, [InstrStage<1, [R_WX_PORT]>], [1,1,1,1]>,
454452
InstrItinData<II_CLB, [InstrStage<1, [R_WX_PORT]>], [1,1,1]>,

‎llvm/test/CodeGen/AIE/aie2/BinaryOutput/mov_mv_add.mir

+3-3
Original file line numberDiff line numberDiff line change
@@ -56,9 +56,9 @@ body: |
5656
$r0 = ADD_NC $r5, 31
5757
$r1 = ADD_NC $r5, -32
5858
$r31 = ADD_NC $r5, 20
59-
$r0 = ADD_NC_GPR $r5, 31
60-
$r1 = ADD_NC_GPR $r5, -32
61-
$r31 = ADD_NC_GPR $r5, 20
59+
$r0 = ADD_NC $r5, 31
60+
$r1 = ADD_NC $r5, -32
61+
$r31 = ADD_NC $r5, 20
6262
$p0 = ADD_NC $r5, 10
6363
$p7 = ADD_NC $r5, -23
6464
$sp = ADD_NC $r5, 21

‎llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-llvm-start-loop-iterations.mir

+2-2
Original file line numberDiff line numberDiff line change
@@ -38,8 +38,8 @@ body: |
3838
; CHECK: liveins: $r0
3939
; CHECK-NEXT: {{ $}}
4040
; CHECK-NEXT: [[COPY:%[0-9]+]]:er = COPY $r0
41-
; CHECK-NEXT: [[ADD_NC_GPR:%[0-9]+]]:er = ADD_NC_GPR [[COPY]], -1
42-
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[ADD_NC_GPR]]
41+
; CHECK-NEXT: [[ADD_NC:%[0-9]+]]:er = ADD_NC [[COPY]], -1
42+
; CHECK-NEXT: PseudoRET implicit $lr, implicit [[ADD_NC]]
4343
%0:gprregbank(s32) = COPY $r0
4444
%1:gprregbank(s32) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.start.loop.iterations), %0(s32)
4545
PseudoRET implicit $lr, implicit %1

‎llvm/test/CodeGen/AIE/aie2/hardware-loops/zol-nested-loop.mir

+2-2
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ body: |
2020
; CHECK-NEXT: {{ $}}
2121
; CHECK-NEXT: renamable $r2 = LDA_dms_lda_idx_imm renamable $p0, 0 :: (load (s32))
2222
; CHECK-NEXT: renamable $r3 = MOV_RLC_imm10_pseudo 0
23-
; CHECK-NEXT: renamable $r0 = ADD_NC_GPR killed renamable $r0, -1
23+
; CHECK-NEXT: renamable $r0 = ADD_NC killed renamable $r0, -1
2424
; CHECK-NEXT: renamable $r4 = MOV_RLC_imm10_pseudo 2
2525
; CHECK-NEXT: renamable $p2 = MOVXM_lng_cg %bb.1
2626
; CHECK-NEXT: {{ $}}
@@ -63,7 +63,7 @@ body: |
6363
6464
renamable $r2 = LDA_dms_lda_idx_imm renamable $p0, 0 :: (load (s32))
6565
renamable $r3 = MOV_RLC_imm10_pseudo 0
66-
renamable $r0 = ADD_NC_GPR killed renamable $r0, -1
66+
renamable $r0 = ADD_NC killed renamable $r0, -1
6767
renamable $r4 = MOV_RLC_imm10_pseudo 2
6868
renamable $p2 = MOVXM_lng_cg %bb.1
6969

‎llvm/test/CodeGen/AIE/aie2/schedule/loopaware/non-dedicated-exit.mir

+2-2
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,7 @@ body: |
3838
; CHECK-NEXT: successors: %bb.2(0x80000000)
3939
; CHECK-NEXT: liveins: $p0, $p1, $r0
4040
; CHECK-NEXT: {{ $}}
41-
; CHECK-NEXT: $r0 = ADD_NC_GPR killed $r0, -1
41+
; CHECK-NEXT: $r0 = ADD_NC killed $r0, -1
4242
; CHECK-NEXT: {{ $}}
4343
; CHECK-NEXT: bb.2:
4444
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
@@ -76,7 +76,7 @@ body: |
7676
successors: %bb.2(0x80000000)
7777
liveins: $p0, $p1, $r0
7878
79-
$r0 = ADD_NC_GPR $r0, -1
79+
$r0 = ADD_NC $r0, -1
8080
8181
bb.2:
8282
successors: %bb.2(0x7c000000), %bb.3(0x04000000)

‎llvm/test/CodeGen/AIE/aie2/schedule/loopaware/short-hwloop.mir

+2-2
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ body: |
3434
; CHECK-NEXT: {{ $}}
3535
; CHECK-NEXT: BUNDLE implicit-def $r1, implicit-def $r0, implicit killed $r1 {
3636
; CHECK-NEXT: $r1 = MUL_mul_r_rr killed $r1, $r1
37-
; CHECK-NEXT: $r0 = ADD_NC_GPR internal $r1, 1
37+
; CHECK-NEXT: $r0 = ADD_NC internal $r1, 1
3838
; CHECK-NEXT: }
3939
; CHECK-NEXT: $p0 = ST_dms_sts_pstm_nrm_imm $r0, killed $p0, 4
4040
; CHECK-NEXT: PseudoLoopEnd %bb.2, %bb.1
@@ -61,7 +61,7 @@ body: |
6161
bb.1:
6262
liveins: $p0, $r0, $r1, $r2
6363
successors: %bb.1, %bb.2
64-
$r0 = ADD_NC_GPR $r1, 1
64+
$r0 = ADD_NC $r1, 1
6565
$p0 = ST_dms_sts_pstm_nrm_imm $r0, $p0, 4
6666
$r1 = MUL_mul_r_rr $r1, $r1
6767
PseudoLoopEnd %bb.2, %bb.1

‎llvm/test/CodeGen/AIE/aie2/schedule/resource/r_wm.mir

+16-16
Original file line numberDiff line numberDiff line change
@@ -50,29 +50,29 @@ body: |
5050
...
5151

5252
---
53-
name: E2_VEXTRACT_E1_ADD_NC_GPR
53+
name: E2_VEXTRACT_E1_ADD_NC_R
5454
alignment: 16
5555
body: |
5656
bb.0.entry:
57-
; CHECK-LABEL: name: E2_VEXTRACT_E1_ADD_NC_GPR
57+
; CHECK-LABEL: name: E2_VEXTRACT_E1_ADD_NC_R
5858
; CHECK: $r2 = VEXTRACT_S32 killed $x2, killed $r16
5959
; CHECK-NEXT: NOP
60-
; CHECK-NEXT: $r3 = ADD_NC_GPR killed $r4, -32
60+
; CHECK-NEXT: $r3 = ADD_NC killed $r4, -32
6161
$r2 = VEXTRACT_S32 $x2, $r16
62-
$r3 = ADD_NC_GPR $r4, -32
62+
$r3 = ADD_NC $r4, -32
6363
...
6464

6565
---
66-
name: E2_VCMP_E1_ADD_NC_GPR
66+
name: E2_VCMP_E1_ADD_NC_R
6767
alignment: 16
6868
body: |
6969
bb.0.entry:
70-
; CHECK-LABEL: name: E2_VCMP_E1_ADD_NC_GPR
70+
; CHECK-LABEL: name: E2_VCMP_E1_ADD_NC_R
7171
; CHECK: $r16 = VLT_BF16 killed $x0, killed $x5
7272
; CHECK-NEXT: NOP
73-
; CHECK-NEXT: $r3 = ADD_NC_GPR killed $r4, -32
73+
; CHECK-NEXT: $r3 = ADD_NC killed $r4, -32
7474
$r16 = VLT_BF16 $x0, $x5
75-
$r3 = ADD_NC_GPR $r4, -32
75+
$r3 = ADD_NC $r4, -32
7676
...
7777

7878
---
@@ -115,29 +115,29 @@ body: |
115115
...
116116

117117
---
118-
name: E2_VMAX_LT_E1_ADD_NC_GPR
118+
name: E2_VMAX_LT_E1_ADD_NC_R
119119
alignment: 16
120120
body: |
121121
bb.0.entry:
122-
; CHECK-LABEL: name: E2_VMAX_LT_E1_ADD_NC_GPR
122+
; CHECK-LABEL: name: E2_VMAX_LT_E1_ADD_NC_R
123123
; CHECK: $x0, $r22 = VMAX_LT_BF16 killed $x5, killed $x3
124124
; CHECK-NEXT: NOP
125-
; CHECK-NEXT: $r3 = ADD_NC_GPR killed $r4, -32
125+
; CHECK-NEXT: $r3 = ADD_NC killed $r4, -32
126126
$x0, $r22 = VMAX_LT_BF16 $x5, $x3
127-
$r3 = ADD_NC_GPR $r4, -32
127+
$r3 = ADD_NC $r4, -32
128128
...
129129

130130
---
131-
name: E2_VMAXDIFF_LT_E1_ADD_NC_GPR
131+
name: E2_VMAXDIFF_LT_E1_ADD_NC_R
132132
alignment: 16
133133
body: |
134134
bb.0.entry:
135-
; CHECK-LABEL: name: E2_VMAXDIFF_LT_E1_ADD_NC_GPR
135+
; CHECK-LABEL: name: E2_VMAXDIFF_LT_E1_ADD_NC_R
136136
; CHECK: $x0, $r22 = VMAXDIFF_LT_S16 killed $x5, killed $x3
137137
; CHECK-NEXT: NOP
138-
; CHECK-NEXT: $r3 = ADD_NC_GPR killed $r4, -32
138+
; CHECK-NEXT: $r3 = ADD_NC killed $r4, -32
139139
$x0, $r22 = VMAXDIFF_LT_S16 $x5, $x3
140-
$r3 = ADD_NC_GPR $r4, -32
140+
$r3 = ADD_NC $r4, -32
141141
...
142142

143143
# VEQZ accesses WM write port in cycle 2, MOV in cycle 1

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