Martien.physreg liveranges #747

martien-de-jong · 2025-12-31T10:00:13Z

This is a POC of register allocation during postpipelining.

We add

RegDefUseTracker, taking care of virtualizing safe live ranges,
SchedulingInterpreter, computing register live ranges based on scheduled pipeline timing
PostRegAlloc, using the two to allocate the virtual registers after postpipelining.

F-Stuckmann · 2026-01-05T09:38:14Z

llvm/lib/Target/AIE/AIERegDefUseTracker.cpp

+    return true;
+
+  // Check if Reg1 is a sub-register of Reg2
+  for (MCSubRegIterator SubRegIt(Reg2, TRI, /*IncludeSelf=*/false);


We could think about using RegUnits then we do not have to iterate through sub and super registers.

solved in a trailing commit.

Also for virtual registers. For architectures where latencies can go negative, this has impact on RecMII

This is abstracting the live ranges to be used by PostRegAlloc

This module analyses live ranges of physical registers that can be safely reallocated in a basic block. It supplies facilities to rewrite to virtual registers and to restore the original allocation.

This module produces an EventSchedule from the instructions and their issue cycle. The event schedule contains the read and write events of the virtual registers occuring in the instructions ordered in the processor pipeline stage timeline. From the EventSchedule the modulo liveranges for a particular II can be constructed. These represent the lanes of each register that are live at a particular point.

This is a dedicated register allocator for use by the postpipeliner

martien-de-jong · 2026-01-08T12:15:05Z

llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h

    /// register. There may be multiple current definitions for a register with
    /// disjunct lanemasks.
-    VReg2SUnitMultiMap CurrentVRegDefs;
+    VReg2SUnitOperIdxMultiMap CurrentVRegDefs;


This was asymmetric between Uses and Defs. We need the operand index of the outstanding defs to compute operand latencies.

martien-de-jong · 2026-01-08T12:18:13Z

llvm/lib/Target/AIE/AIEMaxLatencyFinder.cpp

+
+  // Use TRI's regsOverlap which handles both physical and virtual registers,
+  // including subregisters and lane masks
+  return TRI->regsOverlap(SrcReg, DstReg);


I guess this was only needed transiently, but it looks really good.

martien-de-jong · 2026-01-08T12:21:55Z

llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp

-        PostSWP->isPostPipelineCandidate(*TheBlock))
-      staticallyMaterializeMultiSlotInstructions(*TheBlock, HR);
+        PostSWP->isPostPipelineCandidate(*TheBlock)) {
+      staticallyMaterializeMultiSlotInstructions(*TheBlock, HR, MaterializeAll);


Would have been nice to be able to skip the scheduler before postpipelining. Sadly, the scheduler sometimes makes better decisions.

martien-de-jong · 2026-01-08T12:26:08Z

llvm/lib/Target/AIE/AIEScheduleInterpreter.cpp

+    for (int T = 0; T < II; ++T) {
+      LaneBitmask Mask = LanesByOffset[T];
+      if (Mask.any()) {
+        // Show a simple indicator - could be enhanced to show actual lanes


Indeed. Full lanemasks are bulky though.

martien-de-jong · 2026-01-08T12:33:45Z

llvm/lib/Target/AIE/AIEPostRegAlloc.cpp

+
+  // Score based on total lane usage (which already incorporates duration)
+  // Add a small bonus for max lanes to prioritize wide registers
+  unsigned Score = TotalLanes * 10 + MaxLanes;


This score determines the order in which the virtregs are going to be allocated. I think this could be improved, or we could use a few different scoring functions. It's good enough for our motivating unittest though.

A 'loop through strategies" is forthcoming.

martien-de-jong · 2026-01-08T12:38:20Z

llvm/lib/Target/AIE/AIEPostRegAlloc.cpp

+  const TargetRegisterClass *RC = MRI.getRegClass(VReg);
+
+  // Get available physical registers from RegTracker
+  const auto &AvailableRegs = RegTracker.getAvailablePhysRegs();


This references a temporary object. Will be fixed in a future push

In that same push, we compute the available registers only once and pass it down.

martien-de-jong · 2026-01-08T14:07:46Z

llvm/lib/Target/AIE/AIEPostRegAlloc.cpp

+bool AIEPostRegAlloc::tryAllocate(
+    const DenseMap<unsigned, AIE::LaneMaskVector> &LiveLanesByVReg, int II,
+    const RegLiveRangeTracker &RegTracker, const TargetRegisterInfo &TRI,
+    const MachineRegisterInfo &MRI, AllocState &State, bool UseBestFit) {


BestFit is a hallucination of AI. It will be removed.

martien-de-jong · 2026-01-08T14:12:49Z

llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp

+static cl::opt<bool> TestRegDefUseTracker(
+    "aie-test-regdefuse-tracker", cl::Hidden, cl::init(false),
+    cl::desc("[AIE] TEST MODE: Run RegDefUseTracker analysis on all loops "
+             "(for testing only)"));


This is accommodating a dump for the early stages of live range analysis.

martien-de-jong · 2026-01-08T14:14:59Z

llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp

+
+void BlockState::restorePipelining() {
+  // Restore to the original allocation of the virtual registers
+  RegTracker->restoreOriginalPhysRegs();


These registers were used by the scheduler whose result we're going to use as a fallback.

We sandwich graph construction and pipelining between a rewrite to virtual registers and a restoration of those. This is a no-op if pipelining fails. If it succeeds, it has found and applied a valid register allocation for the virtual registers that were introduced. The virtualization is controlled by an option which defaults to false, which kept existing references the same.

martien-de-jong · 2026-01-13T14:05:23Z

llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp

-  switch (updateFixPoint(BS)) {
+  const auto Stage = updateFixPoint(BS);
+  BS.FixPoint.Stage = Stage;
+  switch (Stage) {


I will separate this out. It's just cosmetics to return a state and only save it in the top call.

martien-de-jong · 2026-01-13T14:15:51Z

llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp

+    BS.FixPoint.PipelinerMode = firstPipelinerMode();
+    if (BS.FixPoint.PipelinerMode != PostPipelinerMode::None) {
+      return SchedulingStage::Pipelining;
+    }


This looks a bit weird: we have been pipelining and are trying to restore to the first allowed pipelinermode for the next II. This should be invariant, so I don't think we can get None here. Perhaps assert.

martien-de-jong · 2026-01-13T14:21:24Z

llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp

+
+  // For virtual mode, re-analyze and virtualize
+  if (FixPoint.PipelinerMode == PostPipelinerMode::Virtual) {
+    // RegTracker might not exist if we have multiple regions


Someone missed that we can't do physical mode either if we have more than one region.
I would hope that RegTracker is always there for a SWP candidate.

martien-de-jong requested review from F-Stuckmann, SagarMaheshwari99, abhinay-anubola, abnikant, andcarminati, katerynamuts, khallouh, konstantinschwarz, mludevid, niwinanto and stephenneuendorffer as code owners December 31, 2025 10:00

martien-de-jong marked this pull request as draft December 31, 2025 10:00

F-Stuckmann reviewed Jan 5, 2026

View reviewed changes

[AIE][POSTPIPELINER] Register info in DAG dump

a4d92de

martien-de-jong force-pushed the martien.physreg-liveranges branch from cf979b2 to cc8fca8 Compare January 6, 2026 17:12

Martien de Jong added 7 commits January 8, 2026 10:45

[ScheduleDAGInstr] Compute accurate latencies for Anti dependencies

6a7eb6d

Also for virtual registers. For architectures where latencies can go negative, this has impact on RecMII

{AIE] Generalize MaxLatencyFinder for virtual registers

7a380fe

[AIE] full MSP materialization based on slot statistics

db108fa

[AIE] Add LaneMaskVector

d4a32d0

This is abstracting the live ranges to be used by PostRegAlloc

[AIE] Add RegDefUseTracker

7bca037

This module analyses live ranges of physical registers that can be safely reallocated in a basic block. It supplies facilities to rewrite to virtual registers and to restore the original allocation.

[AIE] Add AIEPostRegAlloc

329718b

This is a dedicated register allocator for use by the postpipeliner

martien-de-jong force-pushed the martien.physreg-liveranges branch from cc8fca8 to 33264be Compare January 8, 2026 10:48

martien-de-jong marked this pull request as ready for review January 8, 2026 11:13

martien-de-jong commented Jan 8, 2026

View reviewed changes

martien-de-jong force-pushed the martien.physreg-liveranges branch from 7930abc to dcc908c Compare January 13, 2026 12:49

martien-de-jong commented Jan 13, 2026

View reviewed changes

Martien.physreg liveranges #747

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Martien.physreg liveranges #747

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martien-de-jong commented Dec 31, 2025 •

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