[AIEX] Unified Opcodes across Subtargets

llvm/lib/Target/AIE/AIEBaseTarget.td

@@ -0,0 +1,83 @@
+//===-- AIEBaseTarget.td - Shared AIE target definition ----*- tablegen -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2026 Advanced Micro Devices, Inc. or its affiliates
+//
+//===----------------------------------------------------------------------===//
+//
+// Shared TableGen compilation for the canonical AIE:: opcode namespace.
+// All architecture-specific AIE targets are expected to produce identical
+// enum values for:
+//   1. LLVM generic opcodes from TargetOpcodes.def
+//   2. AIE generic opcodes from AIEInstrGISel.td
+//
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/Target.td"
+include "llvm/Target/AIETarget.td"
+include "llvm/Target/CodeGenFormat.td"
+
+// Minimal register definition required by the gen-instr-info backend.
+// Only enum values from this compilation are consumed.
+def AIEBaseTargetReg : Register<"r0">;
+def AIEBaseTargetGPR
+    : RegisterClass<"AIE", [i32], 32, (add AIEBaseTargetReg)>;
+
+class AIEGenericInstruction : GenericInstruction {
+  let Namespace = "AIEBase";
+}
+include "AIEInstrGISel.td"
+
+// Shared pseudo instructions present in all AIE targets.
+// Must be defined here so AIEBase enum values match the subtargets.
+let Namespace = "AIEBase", isPseudo = true, isCodeGenOnly = true in {
+  def ADJCALLSTACKDOWN : Instruction {
+    let hasSideEffects = false;
+    let mayLoad = false;
+    let mayStore = false;
+    let OutOperandList = (outs);
+    let InOperandList = (ins i32imm:$amt1, i32imm:$amt2);
+    let AsmString = "";
+    let Pattern = [];
+  }
+  def ADJCALLSTACKUP : Instruction {
+    let hasSideEffects = false;
+    let mayLoad = false;
+    let mayStore = false;
+    let OutOperandList = (outs);
+    let InOperandList = (ins i32imm:$amt1, i32imm:$amt2);
+    let AsmString = "";
+    let Pattern = [];
+  }
+  def CYCLE_SEPARATOR : Instruction {
+    let hasSideEffects = false;
+    let mayLoad = false;
+    let mayStore = false;
+    let OutOperandList = (outs);
+    let InOperandList = (ins);
+    let AsmString = "";
+    let Pattern = [];
+    let isMeta = true;
+  }
+  def DelayedSchedBarrier : Instruction {
+    let hasSideEffects = false;
+    let mayLoad = false;
+    let mayStore = false;
+    let OutOperandList = (outs);
+    let InOperandList = (ins);
+    let AsmString = "";
+    let Pattern = [];
+    let isMeta = true;
+  }
+}
+
+def AIEBaseTargetInstrInfo : InstrInfo {
+  let guessInstructionProperties = 0;
+}
+
+def AIEBaseTarget : Target {
+  let InstructionSet = AIEBaseTargetInstrInfo;
+}

llvm/lib/Target/AIE/AIEBaseTargetOpcodes.h

@@ -0,0 +1,22 @@
+//===-- AIEBaseTargetOpcodes.h - Shared opcode namespace -----*- C++ -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2026 Advanced Micro Devices, Inc. or its affiliates
+//
+//===----------------------------------------------------------------------===//
+//
+// Exposes the canonical AIE:: namespace enum values produced by
+// AIEBaseTarget.td.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AIE_AIEBASETARGETOPCODES_H
+#define LLVM_LIB_TARGET_AIE_AIEBASETARGETOPCODES_H
+
+#define GET_INSTRINFO_ENUM
+#include "AIEBaseTargetGenInstrInfo.inc"
+
+#endif // LLVM_LIB_TARGET_AIE_AIEBASETARGETOPCODES_H

llvm/lib/Target/AIE/AIEGenericOpcode.h

@@ -0,0 +1,53 @@
+//===-- AIEGenericOpcode.h - Cross-target opcode parity --------*- C++ -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2026 Advanced Micro Devices, Inc. or its affiliates
+//
+//===----------------------------------------------------------------------===//
+//
+// Always-on opcode parity validation between AIEBaseTarget and each AIE
+// subtarget.  Provides the AIE_CHECK_OPCODE_ macro used by each target's
+// InstrInfo constructor to verify enum value equality.
+//
+// Usage in each target's InstrInfo.cpp:
+//
+//   #include "AIEGenericOpcode.h"
+//
+//   namespace {
+//   void verifyOpcodeParity() {
+//     #define HANDLE_TARGET_OPCODE(OPC) \
+//       AIE_CHECK_OPCODE_(AIEBase, MyTargetNS, OPC)
+//     #define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC)
+//     #include "llvm/Support/TargetOpcodes.def"
+//
+//     #define AIE_GENERIC_OPCODE(OPC) \
+//       AIE_CHECK_OPCODE_(AIEBase, MyTargetNS, OPC)
+//     #include "AIEGenericOpcodeList.def"
+//   }
+//   } // anonymous namespace
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_AIE_AIEGENERICOPCODE_H
+#define LLVM_LIB_TARGET_AIE_AIEGENERICOPCODE_H
+
+#include "AIEBaseTargetOpcodes.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/Support/ErrorHandling.h"
+
+/// Check a single opcode for parity between BASE_NS and TARGET_NS.
+/// Hard-fails via report_fatal_error on mismatch in all build modes.
+#define AIE_CHECK_OPCODE_(BASE_NS, TARGET_NS, OPC)                             \
+  if (static_cast<unsigned>(BASE_NS::OPC) !=                                   \
+      static_cast<unsigned>(TARGET_NS::OPC))                                   \
+    llvm::report_fatal_error(                                                  \
+        llvm::Twine("opcode parity mismatch: " #BASE_NS "::" #OPC " (") +      \
+            llvm::Twine(static_cast<unsigned>(BASE_NS::OPC)) +                 \
+            ") != " #TARGET_NS "::" #OPC " (" +                                \
+            llvm::Twine(static_cast<unsigned>(TARGET_NS::OPC)) + ")",          \
+        /*gen_crash_diag=*/false);
+
+#endif // LLVM_LIB_TARGET_AIE_AIEGENERICOPCODE_H

llvm/lib/Target/AIE/AIEGenericOpcodeList.def

@@ -0,0 +1,48 @@
+//===-- AIEGenericOpcodeList.def ----------------------------------------===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2026 Advanced Micro Devices, Inc. or its affiliates
+//
+//===----------------------------------------------------------------------===//
+//
+// List of AIE generic opcodes from AIEInstrGISel.td.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef AIE_GENERIC_OPCODE
+#define AIE_GENERIC_OPCODE(OPC)
+#endif
+
+AIE_GENERIC_OPCODE(G_AIE_POSTINC_LOAD)
+AIE_GENERIC_OPCODE(G_AIE_POSTINC_ZEXTLOAD)
+AIE_GENERIC_OPCODE(G_AIE_POSTINC_SEXTLOAD)
+AIE_GENERIC_OPCODE(G_AIE_OFFSET_LOAD)
+AIE_GENERIC_OPCODE(G_AIE_OFFSET_ZEXTLOAD)
+AIE_GENERIC_OPCODE(G_AIE_OFFSET_SEXTLOAD)
+AIE_GENERIC_OPCODE(G_AIE_POSTINC_2D_LOAD)
+AIE_GENERIC_OPCODE(G_AIE_POSTINC_2D_ZEXTLOAD)
+AIE_GENERIC_OPCODE(G_AIE_POSTINC_2D_SEXTLOAD)
+AIE_GENERIC_OPCODE(G_AIE_POSTINC_3D_LOAD)
+AIE_GENERIC_OPCODE(G_AIE_POSTINC_3D_ZEXTLOAD)
+AIE_GENERIC_OPCODE(G_AIE_POSTINC_3D_SEXTLOAD)
+AIE_GENERIC_OPCODE(G_AIE_POSTINC_STORE)
+AIE_GENERIC_OPCODE(G_AIE_OFFSET_STORE)
+AIE_GENERIC_OPCODE(G_AIE_POSTINC_2D_STORE)
+AIE_GENERIC_OPCODE(G_AIE_POSTINC_3D_STORE)
+AIE_GENERIC_OPCODE(G_AIE_ZEXT_EXTRACT_VECTOR_ELT)
+AIE_GENERIC_OPCODE(G_AIE_SEXT_EXTRACT_VECTOR_ELT)
+AIE_GENERIC_OPCODE(G_AIE_INSERT_VECTOR_ELT)
+AIE_GENERIC_OPCODE(G_AIE_ADD_VECTOR_ELT_HI)
+AIE_GENERIC_OPCODE(G_AIE_BROADCAST_VECTOR)
+AIE_GENERIC_OPCODE(G_AIE_PAD_VECTOR_UNDEF)
+AIE_GENERIC_OPCODE(G_AIE_UNPAD_VECTOR)
+AIE_GENERIC_OPCODE(G_AIE_VSEL)
+AIE_GENERIC_OPCODE(G_AIE_VSHIFT_RIGHT)
+AIE_GENERIC_OPCODE(G_AIE_EXTRACT_SUBVECTOR)
+AIE_GENERIC_OPCODE(G_AIE_SHUFFLE_VECTOR)
+AIE_GENERIC_OPCODE(G_AIE_VECTOR_ICMP)
+
+#undef AIE_GENERIC_OPCODE

llvm/lib/Target/AIE/AIEInstrGISel.td

@@ -4,7 +4,7 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+// (c) Copyright 2023-2026 Advanced Micro Devices, Inc. or its affiliates
 //
 //===----------------------------------------------------------------------===//
 //
@@ -110,8 +110,8 @@ def G_AIE_UNPAD_VECTOR : AIEGenericInstruction {
   let hasSideEffects = false;
 }
 
-// Select between the words of two vectors. The selection is performed between 
-// each word in the position corresponding to the bit position in 
+// Select between the words of two vectors. The selection is performed between
+// each word in the position corresponding to the bit position in
 // the sel parameter.
 def G_AIE_VSEL : AIEGenericInstruction {
   let OutOperandList = (outs type0:$dst);
@@ -127,14 +127,14 @@ def G_AIE_VSHIFT_RIGHT : AIEGenericInstruction {
   let hasSideEffects = false;
 }
 
-// Extract 32-bit or 64-bit subvector. The native source type1 is 512 bits. 
+// Extract 32-bit or 64-bit subvector. The native source type1 is 512 bits.
 def G_AIE_EXTRACT_SUBVECTOR : AIEGenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type1:$src, type2:$idx);
   let hasSideEffects = false;
 }
 
-// Corresponds to AIE shuffle vector. 
+// Corresponds to AIE shuffle vector.
 def G_AIE_SHUFFLE_VECTOR : AIEGenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src0, type0:$src1, type1:$mode);

llvm/lib/Target/AIE/AIESharedPseudos.td

@@ -0,0 +1,108 @@
+//===-- AIESharedPseudos.td - Shared pseudo instructions ---*- tablegen -*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2026 Advanced Micro Devices, Inc. or its affiliates
+//
+//===----------------------------------------------------------------------===//
+//
+// Shared pseudo instruction classes for instructions that exist with the same
+// name across AIE targets. These classes share the same name across AIE targets to be in
+// Layer 2 of the enum layout, guaranteeing identical enum values across all
+// target compilations.
+//
+// This file must be included AFTER the target's InstrFormats.td, so that
+// `Pseudo` resolves to the target-specific class (e.g., AIE2Inst or AIE2PInst
+// based).
+//
+//===----------------------------------------------------------------------===//
+
+// Base class for all shared pseudos. Provides a base class for shared pseudo instructions in
+// enum placement in Layer 2.
+class AIESharedPseudo<dag outs, dag ins, string opcodestr = "",
+                      string argstr = "">
+    : Pseudo<outs, ins, opcodestr, argstr> {
+}
+
+//===----------------------------------------------------------------------===//
+// Identical across targets (no parameters needed)
+//===----------------------------------------------------------------------===//
+
+class AIEDelayedSchedBarrier : AIESharedPseudo<(outs), (ins)> {
+  let isMeta = true;
+  let hasSideEffects = false;
+  let mayLoad = false;
+  let mayStore = false;
+}
+
+class AIECycleSeparator : AIESharedPseudo<(outs), (ins)> {
+  let isMeta = true;
+  let hasSideEffects = false;
+  let mayLoad = false;
+  let mayStore = false;
+}
+
+class AIELoopDec
+    : AIESharedPseudo<(outs eR:$dst), (ins eR:$src),
+                      "loop_dec", "${dst}, ${src}"> {
+  let hasSideEffects = false;
+  let mayLoad = false;
+  let mayStore = false;
+  let Defs = [srCarry];
+}
+
+class AIELoopJNZ
+    : AIESharedPseudo<(outs), (ins eR:$tc, eP:$target),
+                      "loop_jnz", "${tc}, ${target}"> {
+  let hasSideEffects = false;
+  let mayLoad = false;
+  let mayStore = false;
+  let isBranch = true;
+  let isIndirectBranch = true;
+  let isTerminator = true;
+}
+
+//===----------------------------------------------------------------------===//
+// Parameterized (operand types differ per target)
+//===----------------------------------------------------------------------===//
+
+class AIELoopStart<Operand adj_type>
+    : AIESharedPseudo<(outs), (ins eR:$src, adj_type:$adj),
+                      "loop_start", "${src}, ${adj}"> {
+  let hasSideEffects = true;
+  let mayLoad = false;
+  let mayStore = false;
+  let isNotDuplicable = true;
+}
+
+class AIEPseudoLoopEnd<Operand addr_type>
+    : AIESharedPseudo<(outs), (ins addr_type:$lastInstr, addr_type:$target),
+                      "pseudo_loop_end", "${lastInstr}, ${target}"> {
+  let hasSideEffects = true;
+  let mayLoad = false;
+  let mayStore = false;
+  let isNotDuplicable = true;
+  let isBranch = true;
+  let isTerminator = true;
+  let isMeta = true;
+}
+
+class AIEAdjCallStackDown<Register sp_reg>
+    : AIESharedPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2)> {
+  let hasSideEffects = false;
+  let mayLoad = false;
+  let mayStore = false;
+  let Defs = [sp_reg];
+  let Uses = [sp_reg];
+}
+
+class AIEAdjCallStackUp<Register sp_reg>
+    : AIESharedPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2)> {
+  let hasSideEffects = false;
+  let mayLoad = false;
+  let mayStore = false;
+  let Defs = [sp_reg];
+  let Uses = [sp_reg];
+}

llvm/lib/Target/AIE/CMakeLists.txt

@@ -96,6 +96,10 @@ tablegen(LLVM AIE2PSGenPostLegalizerGICustomCombiner.inc -gen-global-isel-combin
               -combiners="AIE2PSPostLegalizerCustomCombiner")
 tablegen(LLVM AIE2PSGenAsmMatcher.inc -gen-asm-matcher)
 
+#aie-base-target (shared AIE:: namespace for generic opcodes)
+set(LLVM_TARGET_DEFINITIONS AIEBaseTarget.td)
+tablegen(LLVM AIEBaseTargetGenInstrInfo.inc -gen-instr-info)
+
 add_public_tablegen_target(AIECommonTableGen)
 
 add_llvm_target(AIECodeGen

llvm/lib/Target/AIE/aie1/AIE1InstrInfo.td

@@ -4,7 +4,7 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
+// (c) Copyright 2023-2026 Advanced Micro Devices, Inc. or its affiliates
 //
 //===----------------------------------------------------------------------===//
 //
@@ -2409,6 +2409,21 @@ def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                               [(callseq_end timm:$amt1, timm:$amt2)]>;
 }
 
+// Shared pseudo instructions for opcode parity with AIE2/AIE2P.
+def CYCLE_SEPARATOR  : Pseudo<(outs), (ins), []> {
+  let isMeta = true;
+  let hasSideEffects = false;
+  let mayLoad = false;
+  let mayStore = false;
+}
+def DelayedSchedBarrier : Pseudo<(outs), (ins), []> {
+  let isMeta = true;
+  let hasSideEffects = false;
+  let mayLoad = false;
+  let mayStore = false;
+}
+
+
 let hasDelaySlot = 1, Itinerary = II_RET in
 let isBarrier = 1, isReturn = 1, isTerminator = 1, Uses = [lr] in
 def PseudoRET : Pseudo<(outs), (ins), [(aie_ret_flag)]>,