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[AIEX] Unified Opcodes across Subtargets #766

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[AIEX] Unified Opcodes across Subtargets #766

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f04d5d6
[AIE] Add shared opcode infrastructure with cross-target parity checks
F-Stuckmann Mar 6, 2026
572445e
[AIE] Add cross-target opcode parity verification
F-Stuckmann Mar 6, 2026
f6f9a81
[AIE] Migrate generic opcode references to shared AIE:: namespace
F-Stuckmann Mar 6, 2026
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42 changes: 17 additions & 25 deletions llvm/lib/Target/AIE/AIE2InstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@
#include "AIE2Subtarget.h"
#include "AIE2TargetMachine.h"
#include "AIEBaseInstrInfo.h"
#include "AIEGenericOpcode.h"
#include "AIEHazardRecognizer.h"
#include "AIEMachineFunctionInfo.h"
#include "AIEMachineScheduler.h"
Expand Down Expand Up @@ -56,11 +57,27 @@ using namespace llvm;
#include "AIE2GenVarInstructionItin.inc"

namespace {
/// Verify that LLVM generic opcodes and AIE generic opcodes have identical
/// enum values in AIEBase and this target's namespace. This ensures shared
/// code using AIE::G_AIE_* constants works correctly across all subtargets.
/// Terminates via report_fatal_error on the first mismatch, in all build modes.
void verifyOpcodeParity() {
#undef HANDLE_TARGET_OPCODE
#undef HANDLE_TARGET_OPCODE_MARKER
#define HANDLE_TARGET_OPCODE(OPC) AIE_CHECK_OPCODE_(AIEBase, AIE2, OPC)
#define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC)
#include "llvm/Support/TargetOpcodes.def"

#define AIE_GENERIC_OPCODE(OPC) AIE_CHECK_OPCODE_(AIEBase, AIE2, OPC)
#include "AIEGenericOpcodeList.def"
}

const AIE2MCFormats AIE2Formats;
} // namespace

AIE2InstrInfo::AIE2InstrInfo()
: AIE2GenInstrInfo(AIE2::ADJCALLSTACKUP, AIE2::ADJCALLSTACKDOWN) {
verifyOpcodeParity();
FormatInterface = &AIE2Formats;
FuncUnitWrapper::setFormatInterface(FormatInterface);
}
Expand Down Expand Up @@ -923,31 +940,6 @@ unsigned AIE2InstrInfo::getCycleSeparatorOpcode() const {
return AIE2::CYCLE_SEPARATOR;
}

unsigned AIE2InstrInfo::getGenericAddVectorEltOpcode() const {
return AIE2::G_AIE_ADD_VECTOR_ELT_HI;
}

unsigned AIE2InstrInfo::getGenericInsertVectorEltOpcode() const {
return AIE2::G_AIE_INSERT_VECTOR_ELT;
}

unsigned AIE2InstrInfo::getGenericExtractVectorEltOpcode(bool SignExt) const {
return SignExt ? AIE2::G_AIE_SEXT_EXTRACT_VECTOR_ELT
: AIE2::G_AIE_ZEXT_EXTRACT_VECTOR_ELT;
}

unsigned AIE2InstrInfo::getGenericPadVectorOpcode() const {
return AIE2::G_AIE_PAD_VECTOR_UNDEF;
}

unsigned AIE2InstrInfo::getGenericUnpadVectorOpcode() const {
return AIE2::G_AIE_UNPAD_VECTOR;
}

unsigned AIE2InstrInfo::getGenericBroadcastVectorOpcode() const {
return AIE2::G_AIE_BROADCAST_VECTOR;
}

unsigned int getVLDSparseOpcode(unsigned int PseudoOpc) {
switch (PseudoOpc) {
case AIE2::PSEUDO_VLD_SPARSE_POP_16_set_low:
Expand Down
6 changes: 0 additions & 6 deletions llvm/lib/Target/AIE/AIE2InstrInfo.h
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Expand Up @@ -54,12 +54,6 @@ class AIE2InstrInfo : public AIE2GenInstrInfo {
Register getMSStatusReg() const override;
Register getPackSignCReg() const override;
Register getUnpackSignCReg() const override;
unsigned getGenericAddVectorEltOpcode() const override;
unsigned getGenericInsertVectorEltOpcode() const override;
unsigned getGenericExtractVectorEltOpcode(bool SignExt) const override;
unsigned getGenericPadVectorOpcode() const override;
unsigned getGenericUnpadVectorOpcode() const override;
unsigned getGenericBroadcastVectorOpcode() const override;
unsigned getCycleSeparatorOpcode() const override;
bool isLock(unsigned Opc) const override;
std::optional<unsigned> getDoneLatency(unsigned) const override;
Expand Down
43 changes: 10 additions & 33 deletions llvm/lib/Target/AIE/AIE2InstrInfo.td
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Expand Up @@ -4,7 +4,7 @@
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
// (c) Copyright 2023-2026 Advanced Micro Devices, Inc. or its affiliates
//
//===----------------------------------------------------------------------===//
//
Expand Down Expand Up @@ -368,6 +368,7 @@ include "AIE2CompositeFormats.td"
// Manual fixes to the auto-generated files
include "AIE2GenFixupInstrInfo.td"
include "AIE2MultiSlotPseudoInstrInfo.td"
include "AIESharedPseudos.td"

//Intrinsics
let Itinerary = II_EVENT, hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
Expand All @@ -380,13 +381,8 @@ let Itinerary = II_RET, hasDelaySlot = true, Uses = [lr],
def RET : AIE2_jump_return_inst_alu <(outs), (ins), "ret lr", ""> ;
}

let isMeta = true, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
def DelayedSchedBarrier : Pseudo<(outs), (ins)>;
}

let isMeta = true, hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
def CYCLE_SEPARATOR : Pseudo<(outs), (ins)>;
}
def DelayedSchedBarrier : AIEDelayedSchedBarrier;
def CYCLE_SEPARATOR : AIECycleSeparator;

// Pseudo instructions for VLD.SPARSE to be expanded after RA.
// They allow us to keep QW registers as non allocatable to avoid
Expand Down Expand Up @@ -492,12 +488,8 @@ def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
[SDNPHasChain, SDNPOutGlue]>;
def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
// Pessimistically assume the stack pointer will be clobbered
let Defs = [SP], Uses = [SP],
hasSideEffects=false, mayLoad=false, mayStore=false in {
def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2)>;
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2)>;
}
def ADJCALLSTACKUP : AIEAdjCallStackUp<SP>;
def ADJCALLSTACKDOWN : AIEAdjCallStackDown<SP>;

// NOPs for each VLIW Slot
let Itinerary = II_NOP, hasSideEffects = 0, mayLoad = 0, mayStore = 0, isSlotNOP = true in {
Expand Down Expand Up @@ -549,27 +541,12 @@ def ST_DS_SPILL : Pseudo<(outs ), (ins eDS:$src, imm12x4:$imm), "st_ds_spill", "

// Loop related Pseudos
// JNZD loops
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Defs = [srCarry] in
def LoopDec :
Pseudo<(outs eR:$dst), (ins eR:$src), "loop_dec", "${dst}, ${src}">;

let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isBranch = 1, isIndirectBranch = 1, isTerminator = true in
def LoopJNZ :
Pseudo<(outs), (ins eR:$tc, eP:$target), "loop_jnz", "${tc}, ${target}">;
def LoopDec : AIELoopDec;
def LoopJNZ : AIELoopJNZ;

// Zero overhead loops
let hasSideEffects = true, mayLoad = false, mayStore = false,
isNotDuplicable = true in {
def LoopStart : Pseudo<(outs), (ins eR:$src, simm6:$adj), "loop_start", "${src}, ${adj}">;

// PseudoLoopEnd represents the terminator of a ZOL. You can view it as a
// conditional branch to the loop body. We make this a meta instruction,
// since it doesn't need to be emitted itself, it only carries info for
// its predecessor bundle
let isBranch = true, isTerminator = true, isMeta = true in
def PseudoLoopEnd : Pseudo<(outs), (ins addr20:$lastInstr, addr20:$target),
"pseudo_loop_end", "${lastInstr}, ${target}">;
}
def LoopStart : AIELoopStart<simm6>;
def PseudoLoopEnd : AIEPseudoLoopEnd<addr20>;

// Pseudo Copy
// Target specific impl. of isCopyInstrImp causes the MOVE to be deleted, the Pseudo is
Expand Down
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