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Enable control packet reconfiguration tests on ci #1275

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13 changes: 10 additions & 3 deletions test/xrt/23_ctrlpkt_config/aie.py
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Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,13 @@ def forward(lhs, rhs):


parser = argparse.ArgumentParser(prog="aie.py")
parser.add_argument(
"--device",
dest="device",
default="npu1",
choices=["npu1", "npu2"],
help="Target device (npu1 or npu2)",
)
parser.add_argument(
"--trace-size",
dest="trace_size",
Expand Down Expand Up @@ -163,7 +170,7 @@ def forward(lhs, rhs):
"air-ping-pong-transform",
"canonicalize",
"cse",
"func.func(air-opt-memtile-dma-bds{device=npu1})",
f"func.func(air-opt-memtile-dma-bds{{device={opts.device}}})",
"canonicalize",
"cse",
]
Expand Down Expand Up @@ -209,7 +216,7 @@ def forward(lhs, rhs):
# ## MLIR-AIR to MLIR-AIE
# ################################################

air_to_aie_pass = "air-to-aie{row-offset=2 col-offset=0 device=npu1 emit-while-loop=true use-pkt-flow-at-shim-dma=true use-lock-race-condition-fix=true"
air_to_aie_pass = f"air-to-aie{{row-offset=2 col-offset=0 device={opts.device} emit-while-loop=true use-pkt-flow-at-shim-dma=true use-lock-race-condition-fix=true"
if opts.trace_size > 0:
air_to_aie_pass = air_to_aie_pass + " insert-trace-packet-flow=true"
air_to_aie_pass = air_to_aie_pass + "}"
Expand All @@ -236,7 +243,7 @@ def forward(lhs, rhs):
"builtin.module("
+ ",".join(
[
"func.func(air-opt-shim-dma-bds{device=npu1})",
f"func.func(air-opt-shim-dma-bds{{device={opts.device}}})",
"air-to-std",
"airrt-to-npu{"
+ f"trace-offset={opts.trace_offset} trace-size={opts.trace_size}"
Expand Down
2 changes: 1 addition & 1 deletion test/xrt/23_ctrlpkt_config/base.mlir → test/xrt/23_ctrlpkt_config/base_npu1.mlir
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
//===- base.mlir -----------------------------------------------*- MLIR -*-===//
//===- base_npu1.mlir -----------------------------------------------*- MLIR -*-===//
//
// Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
// SPDX-License-Identifier: MIT
Expand Down
17 changes: 17 additions & 0 deletions test/xrt/23_ctrlpkt_config/base_npu2.mlir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
//===- base_npu2.mlir -----------------------------------------------*- MLIR -*-===//
//
// Copyright (C) 2024, Advanced Micro Devices, Inc. All rights reserved.
// SPDX-License-Identifier: MIT
//
//===----------------------------------------------------------------------===//

module {
aie.device(npu2) @base {
%tile_0_0 = aie.tile(0, 0)
%tile_0_1 = aie.tile(0, 1)
%tile_0_2 = aie.tile(0, 2)
%tile_0_3 = aie.tile(0, 3)
%tile_0_4 = aie.tile(0, 4)
%tile_0_5 = aie.tile(0, 5)
}
}
14 changes: 7 additions & 7 deletions test/xrt/23_ctrlpkt_config/run_npu1_chess.lit
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Original file line number Diff line number Diff line change
Expand Up @@ -4,10 +4,10 @@
// REQUIRES: ryzen_ai_npu1, valid_xchess_license
// RUN: mkdir -p test_npu1_chess
// RUN: cd test_npu1_chess
// UN: %python %S/aie.py
// UN: aie-opt -aie-generate-column-control-overlay="route-shim-to-tile-ctrl=true" %S/base.mlir -o base_overlay.mlir
// UN: %python aiecc.py --no-xchesscc --no-xbridge --device-name=base --aie-generate-xclbin --xclbin-name=base.xclbin base_overlay.mlir
// UN: aie-opt -aie-generate-column-control-overlay="route-shim-to-tile-ctrl=true" aie.mlir -o aie_overlay.mlir
// UN: %python aiecc.py --no-xchesscc --no-xbridge --device-name=forward_0 --aie-generate-ctrlpkt --ctrlpkt-name=ctrlpkt.bin --ctrlpkt-dma-seq-name=ctrlpkt_dma_seq.bin --aie-generate-npu-insts --npu-insts-name=aie_run_seq.bin aie_overlay.mlir
// UN: g++-13 %S/test.cpp -o test.exe -std=c++23 -Wall %test_utils_flags %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
// UN: %run_on_npu1% ./test.exe -x base.xclbin -k MLIR_AIE -i aie_run_seq.bin -c ctrlpkt_dma_seq.bin -p ctrlpkt.bin -v 2
// RUN: %python %S/aie.py --device npu1
// RUN: aie-opt -aie-generate-column-control-overlay="route-shim-to-tile-ctrl=true" %S/base_npu1.mlir -o base_overlay.mlir
// RUN: %python aiecc.py --xchesscc --xbridge --device-name=base --aie-generate-xclbin --xclbin-name=base.xclbin base_overlay.mlir
// RUN: aie-opt -aie-generate-column-control-overlay="route-shim-to-tile-ctrl=true" aie.mlir -o aie_overlay.mlir
// RUN: %python aiecc.py --xchesscc --xbridge --device-name=forward_0 --aie-generate-ctrlpkt --ctrlpkt-name=ctrlpkt.bin --ctrlpkt-dma-seq-name=ctrlpkt_dma_seq.bin --aie-generate-npu-insts --npu-insts-name=aie_run_seq.bin aie_overlay.mlir
// RUN: g++-13 %S/test.cpp -o test.exe -std=c++23 -Wall %test_utils_flags %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
// RUN: %run_on_npu1% ./test.exe -x base.xclbin -k MLIR_AIE -i aie_run_seq.bin -c ctrlpkt_dma_seq.bin -p ctrlpkt.bin -v 2
16 changes: 8 additions & 8 deletions test/xrt/23_ctrlpkt_config/run_npu1_peano.lit
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Expand Up @@ -4,11 +4,11 @@
// REQUIRES: ryzen_ai_npu1, peano
// RUN: mkdir -p test_npu1_peano
// RUN: cd test_npu1_peano
// UN: %python %S/aie.py
// UN: export PEANO_INSTALL_DIR=%PEANO_INSTALL_DIR
// UN: aie-opt -aie-generate-column-control-overlay="route-shim-to-tile-ctrl=true" %S/base.mlir -o base_overlay.mlir
// UN: %python aiecc.py --no-xchesscc --no-xbridge --device-name=base --aie-generate-xclbin --xclbin-name=base.xclbin base_overlay.mlir
// UN: aie-opt -aie-generate-column-control-overlay="route-shim-to-tile-ctrl=true" aie.mlir -o aie_overlay.mlir
// UN: %python aiecc.py --no-xchesscc --no-xbridge --device-name=forward_0 --aie-generate-ctrlpkt --ctrlpkt-name=ctrlpkt.bin --ctrlpkt-dma-seq-name=ctrlpkt_dma_seq.bin --aie-generate-npu-insts --npu-insts-name=aie_run_seq.bin aie_overlay.mlir
// UN: g++-13 %S/test.cpp -o test.exe -std=c++23 -Wall %test_utils_flags %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
// UN: %run_on_npu1% ./test.exe -x base.xclbin -k MLIR_AIE -i aie_run_seq.bin -c ctrlpkt_dma_seq.bin -p ctrlpkt.bin -v 2
// RUN: %python %S/aie.py --device npu1
// RUN: export PEANO_INSTALL_DIR=%PEANO_INSTALL_DIR
// RUN: aie-opt -aie-generate-column-control-overlay="route-shim-to-tile-ctrl=true" %S/base_npu1.mlir -o base_overlay.mlir
// RUN: %python aiecc.py --no-xchesscc --no-xbridge --device-name=base --aie-generate-xclbin --xclbin-name=base.xclbin base_overlay.mlir
// RUN: aie-opt -aie-generate-column-control-overlay="route-shim-to-tile-ctrl=true" aie.mlir -o aie_overlay.mlir
// RUN: %python aiecc.py --no-xchesscc --no-xbridge --device-name=forward_0 --aie-generate-ctrlpkt --ctrlpkt-name=ctrlpkt.bin --ctrlpkt-dma-seq-name=ctrlpkt_dma_seq.bin --aie-generate-npu-insts --npu-insts-name=aie_run_seq.bin aie_overlay.mlir
// RUN: g++-13 %S/test.cpp -o test.exe -std=c++23 -Wall %test_utils_flags %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
// RUN: %run_on_npu1% ./test.exe -x base.xclbin -k MLIR_AIE -i aie_run_seq.bin -c ctrlpkt_dma_seq.bin -p ctrlpkt.bin -v 2
16 changes: 8 additions & 8 deletions test/xrt/23_ctrlpkt_config/run_npu2_peano.lit
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Original file line number Diff line number Diff line change
Expand Up @@ -4,11 +4,11 @@
// REQUIRES: ryzen_ai_npu2, peano
// RUN: mkdir -p test_npu2_peano
// RUN: cd test_npu2_peano
// UN: %python %S/aie.py
// UN: export PEANO_INSTALL_DIR=%PEANO_INSTALL_DIR
// UN: aie-opt -aie-generate-column-control-overlay="route-shim-to-tile-ctrl=true" %S/base.mlir -o base_overlay.mlir
// UN: %python aiecc.py --no-xchesscc --no-xbridge --device-name=base --aie-generate-xclbin --xclbin-name=base.xclbin base_overlay.mlir
// UN: aie-opt -aie-generate-column-control-overlay="route-shim-to-tile-ctrl=true" aie.mlir -o aie_overlay.mlir
// UN: %python aiecc.py --no-xchesscc --no-xbridge --device-name=forward_0 --aie-generate-ctrlpkt --ctrlpkt-name=ctrlpkt.bin --ctrlpkt-dma-seq-name=ctrlpkt_dma_seq.bin --aie-generate-npu-insts --npu-insts-name=aie_run_seq.bin aie_overlay.mlir
// UN: g++-13 %S/test.cpp -o test.exe -std=c++23 -Wall %test_utils_flags %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
// UN: %run_on_npu1% ./test.exe -x base.xclbin -k MLIR_AIE -i aie_run_seq.bin -c ctrlpkt_dma_seq.bin -p ctrlpkt.bin -v 2
// RUN: %python %S/aie.py --device npu2
// RUN: export PEANO_INSTALL_DIR=%PEANO_INSTALL_DIR
// RUN: aie-opt -aie-generate-column-control-overlay="route-shim-to-tile-ctrl=true" %S/base_npu2.mlir -o base_overlay.mlir
// RUN: %python aiecc.py --no-xchesscc --no-xbridge --device-name=base --aie-generate-xclbin --xclbin-name=base.xclbin base_overlay.mlir
// RUN: aie-opt -aie-generate-column-control-overlay="route-shim-to-tile-ctrl=true" aie.mlir -o aie_overlay.mlir
// RUN: %python aiecc.py --no-xchesscc --no-xbridge --device-name=forward_0 --aie-generate-ctrlpkt --ctrlpkt-name=ctrlpkt.bin --ctrlpkt-dma-seq-name=ctrlpkt_dma_seq.bin --aie-generate-npu-insts --npu-insts-name=aie_run_seq.bin aie_overlay.mlir
// RUN: g++-13 %S/test.cpp -o test.exe -std=c++23 -Wall %test_utils_flags %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem
// RUN: %run_on_npu2% ./test.exe -x base.xclbin -k MLIR_AIE -i aie_run_seq.bin -c ctrlpkt_dma_seq.bin -p ctrlpkt.bin -v 2
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