Project 35: Standalone 3-FPGA Trading Appliance PCB

This project is part of a complete end-to-end trading system:

• Main Repository: fpga-trading-systems
• Project Number: 35 of 35 (for now, more to come)
• Category: PCB Design
• Dependencies: Project 33 (10GBASE-R PHY), Project 34 (Market Data Parser)

---

Platform: Custom PCB (8-layer, 200mm × 180mm, 1U half-width) Technology: KiCad 9 / EasyEDA, 3× Xilinx Kintex-7 XC7K325T Status: Schematic design in progress Role: Hardware platform for the complete 3-FPGA trading pipeline

---

Overview

Custom PCB design for a standalone 3-FPGA trading appliance integrating network ingress (FPGA1), order book management (FPGA2), and strategy execution (FPGA3) into a single 1U-mountable board. The design brings together all RTL from Projects 33-34 onto purpose-built hardware with 10GbE fiber connectivity, inter-FPGA Aurora links, and DDR3 memory.

Architecture reference: ARCHITECTURE-STANDALONE-APPLIANCE-MERGED.md

Board Specifications

• Dimensions: 200mm × 180mm (fits 1U half-width)
• Layers: 8-layer stackup
  • F.Cu (Top Signal)
  • In1.Cu (GND)
  • In2.Cu (Signal)
  • In3.Cu (Power)
  • In4.Cu (Power)
  • In5.Cu (Signal)
  • In6.Cu (GND)
  • B.Cu (Bottom Signal)
• Stack-up: Controlled impedance, 100Ω differential
• Copper Weight: 1oz outer, 2oz inner (power planes)
• Finish: ENIG (gold) for SFP+ and SODIMM contacts
• Min Trace/Space: 4mil/4mil (GTX), 5mil/5mil (general)
• Via Size: 0.3mm drill, 0.6mm pad (standard)

Schematic Structure

The project uses a hierarchical schematic design with the following sheets:

1. Main Sheet (standalone-appliance.kicad_sch)

   • Top-level sheet connecting all subsystems

2. FPGA1 (FPGA1.kicad_sch)

   • XC7K325T module
   • 10GbE MAC and ITCH Parser
   • Symbol Filter
   • Aurora TX to FPGA2

3. FPGA2 (FPGA2.kicad_sch)

   • XC7K325T module + MicroBlaze
   • Order Book (8 symbols)
   • BBO Tracker
   • Aurora RX from FPGA1, TX to FPGA3
   • 1GbE Management Interface
   • DDR3 SODIMM interface

4. FPGA3 (FPGA3.kicad_sch)

   • XC7K325T module
   • RTL XGBoost (100 trees)
   • Market Maker FSM
   • Risk Engine
   • FIX Encoder
   • 10GbE TX
   • Aurora RX from FPGA2

5. Power (Power.kicad_sch)

   • 12V input (barrel jack)
   • Power distribution:
     • VCCINT: 1.0V @ 20A (Buck converter)
     • VCCAUX: 1.8V @ 3A (Buck converter)
     • VCCO: 3.3V @ 5A (Buck converter)
     • MGTAVCC: 1.0V @ 3A (LDO, per FPGA)
     • MGTAVTT: 1.2V @ 2A (LDO, per FPGA)
   • Power supervisor (TPS3808)
   • Decoupling capacitors

6. Clocking (Clocking.kicad_sch)

   • 156.25 MHz LVDS oscillator (GTX reference)
   • 100 MHz oscillator (MicroBlaze)
   • Clock distribution to all FPGAs
   • MMCM configuration

7. Debug (Debug.kicad_sch)

   • FT2232H USB-JTAG/UART
   • 14-pin JTAG header (chained to all 3 FPGAs)
   • USB-C connector
   • Reset button with debounce
   • Status LEDs (RGB × 3, misc × 5)
   • OLED display (SSD1306, I2C)

8. Network (Network.kicad_sch)

   • SFP+ cage × 2 (10GbE IN/OUT)
   • RJ45 MagJack + PHY (1GbE Management)
   • 40-pin expansion header (GPIO, I2C, SPI, UART)

Key Design Rules

GTX Differential Pairs (Inter-FPGA Links)

• Controlled impedance: 100Ω ±10%
• Length matching: ±5 mils within pair
• Via count: Minimize (ideally 0)
• Reference plane: Continuous ground
• AC coupling: 100nF at receiver

DDR3 Signals (FPGA2)

• Fly-by topology for address/command
• Length matching per byte lane
• 50Ω single-ended impedance
• ZQ calibration resistor

Power Distribution

• Solid copper power planes (minimal splits)
• Decoupling: 0.1μF per power pin, 10μF per rail
• Power sequencing: VCCINT → VCCAUX → VCCO

Component Placement Guidelines

Based on the architecture document:

Front Panel:
- SFP+ IN (left)
- SFP+ OUT (center-left)
- RJ45 Management (center)
- USB Debug (center-right)
- Status LEDs (right)
- OLED Display (right)
- Vents (top/bottom)

Rear Panel:
- Fan 1, 2, 3 (exhaust)
- Power 12V DC
- 40-pin Expansion Header

Board Layout:
- FPGA1 (left) → FPGA2 (center) → FPGA3 (right)
- DDR3 SODIMM near FPGA2
- Power regulators distributed
- Clock oscillators central
- Debug components near FPGA2

Thermal Management

• 3× 40mm PWM fans (one per FPGA)
• Temperature sensors (TMP102 × 3)
• FPGA XADC monitoring
• Heatsinks on FPGAs
• Front-to-back airflow

Design Notes

1. JTAG Chain: Single chain connecting FPGA1 → FPGA2 → FPGA3
2. Aurora Links: GTX lanes between FPGA1↔FPGA2 and FPGA2↔FPGA3
3. Power Budget: ~102W typical, 162W max
4. Memory: DDR3 SODIMM (8GB max) on FPGA2 only
5. Reference Design: Based on Alinx AX7325B schematic patterns

Next Steps

1. Complete schematic sheets with actual component symbols
2. Assign footprints to all components
3. Create custom footprints if needed (FPGA modules, connectors)
4. Route critical signals (GTX, DDR3, power)
5. Generate manufacturing files (Gerbers, drill files, BOM)

References

• Architecture Document: ARCHITECTURE-STANDALONE-APPLIANCE-MERGED.md
• Alinx AX7325B schematic (reference for GTX, power, SFP+ circuits)
• DS182: Kintex-7 Data Sheet - FFG900 pinout, power specs
• SFF-8431: SFP+ Specification) - SFP+ cage pinout
• JEDEC DDR3 SDRAM Standard - SODIMM interface timing

---

Related Projects

• 33-10gbe-phy-custom - 10GBASE-R PHY (FPGA1/FPGA3 network)
• 34-tcp-itch-parser - Multi-protocol market data parser (FPGA1 firmware)
• 23-order-book - Order book engine (FPGA2 firmware basis)

---

Status: Schematic design in progress (Power sheet complete, FPGA sheets in progress) Created: January 2026 Author: Adilson Dias

Target Hardware: 3× ALINX AX7325B equivalent (Kintex-7 XC7K325T-2FFG900I)