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Issues list

Vivado transparent memory issue backend:verilog bug toolchain:vivado upstream
#1589 opened May 1, 2025 by piotro888
1
convert used with Component does not handle constant signals backport:v0.5 bug
#1574 opened Apr 14, 2025 by rroohhh
Simulation performance degradation on Amaranth 0.5.x bug
#1541 opened Nov 14, 2024 by tilk 0.6
8
functional enum's do not support specifing a shape bug
#1535 opened Oct 15, 2024 by rroohhh
1
Broken Trigger when for TriggerCombination delay/changed expires at the same time bug
#1508 opened Sep 8, 2024 by purdeaandrei 0.6
2
AsyncFIFO cannot be composed with ResetInserter bug
#1463 opened Jul 27, 2024 by mbikovitsky
2
DriverConflict exception is unhelpful if you use io.Buffer bug
#1433 opened Jun 28, 2024 by whitequark
2
data.Const.__repr__ is very unhelpful for complex structures bug
#1432 opened Jun 28, 2024 by whitequark 0.6
VCD files do not display glitches and can get extremely confusing bug
#1412 opened Jun 19, 2024 by whitequark 0.6
2
Elif without preceding If causes Syntax error when Elif has a complex condition bug
#700 opened Apr 11, 2022 by alanvgreen
4
Memory initializers are ignored when synthesizing with Diamond bug toolchain:diamond unsoundness
#684 opened Mar 12, 2022 by whitequark
2
AsyncFIFO removes data from read domain during read reset bug unsoundness
#683 opened Feb 23, 2022 by Lunaphied
cxxsim: ValueError: 4 is not a valid cxxrtl_type bug simulator:cxxsim
#671 opened Dec 25, 2021 by cestrauss
2
AttributeError when requesting an output pin with a clock constraint bug platform:all
#646 opened Nov 12, 2021 by jfng
3
Time-0 race condition for simulation backend:verilog bug unsoundness
#594 opened Feb 10, 2021 by RobertBaruch
6
platform.add_clock_constraint does not work for instances with lattice diamond for machxo2 bug toolchain:diamond
#546 opened Nov 19, 2020 by anuejn
18
Local clock domain can collide with global domain, causing assert failure bug
#536 opened Nov 7, 2020 by korken89
Document how to use connectors from platform definitions bug
#501 opened Sep 24, 2020 by jfng
2
Out-of-box CXXSim fails on MacOS bug simulator:cxxsim
#495 opened Sep 1, 2020 by BracketMaster
1
Error accessing ResetSignal() bug simulator:pysim
#415 opened Jun 29, 2020 by GuzTech
6
r_data is undefined after a simultaneous write to an empty AsyncFIFO bug platform:all unsoundness
#217 opened Sep 20, 2019 by nmigen-issue-migration
2
ProTip! What’s not been updated in a month: updated:<2025-04-15.