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Minor IMX DDR init clean-up #64

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66bce86
ddr: imx: Remove duplicate includes
pamolloy Mar 3, 2026
3dfd44e
imx: Remove undefined declarations
pamolloy Mar 3, 2026
1a0e233
imx: Remove unused macros
pamolloy Mar 3, 2026
4976088
imx: Remove unnecessary macro argument
pamolloy Mar 3, 2026
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10 changes: 4 additions & 6 deletions arch/arm/include/asm/arch-imx8m/ddr.h
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Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2017 NXP
Expand All @@ -10,10 +10,9 @@
#include <asm/types.h>
#include <asm/arch/imx-regs.h>

#define DDR_PHY_BASE 0x3c000000
#define DDRC_DDR_SS_GPR0 0x3d000000
#define DDRC_IPS_BASE_ADDR_0 0x3f400000
#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000))
#define DDRPHY_MEM(X) (0x3c000000 + (X * 0x2000000) + 0x50000)

struct ddrc_freq {
u32 res0[8];
Expand Down Expand Up @@ -636,7 +635,7 @@
#define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8)
#define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240)

#define DDRPHY_CalBusy(X) (IP2APB_DDRPHY_IPS_BASE_ADDR(X) + 4 * 0x020097)
#define DDRPHY_CalBusy (DDR_PHY_BASE + 4 * 0x020097)

#define DRC_PERF_MON_BASE_ADDR(X) (0x3d800000 + ((X) * 0x2000000))
#define DRC_PERF_MON_CNT0_CTL(X) (DRC_PERF_MON_BASE_ADDR(X) + 0x0)
Expand Down Expand Up @@ -707,7 +706,6 @@
void ddr_load_train_firmware(enum fw_type type);
int ddr_init(struct dram_timing_info *timing_info);
int ddr_cfg_phy(struct dram_timing_info *timing_info);
void load_lpddr4_phy_pie(void);
void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
void *dram_config_save(struct dram_timing_info *info, unsigned long base);
void board_dram_ecc_scrub(void);
Expand Down Expand Up @@ -743,8 +741,8 @@
}

#define dwc_ddrphy_apb_wr(addr, data) \
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data)
reg32_write(DDR_PHY_BASE + ddrphy_addr_remap(addr), data)
#define dwc_ddrphy_apb_rd(addr) \
reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
reg32_read(DDR_PHY_BASE + ddrphy_addr_remap(addr))

#endif
8 changes: 2 additions & 6 deletions arch/arm/include/asm/arch-imx9/ddr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -34,9 +34,6 @@
#define REG_SRC_DPHY_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x20)
#define REG_SRC_DPHY_SINGLE_RESET_SW_CTRL (SRC_DPHY_BASE_ADDR + 0x24)

#define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (DDR_PHY_BASE + ((X) * 0x2000000))
#define DDRPHY_MEM(X) (DDR_PHY_BASE + ((X) * 0x2000000) + 0x50000)

/* PHY State */
enum pstate {
PS0,
Expand Down Expand Up @@ -103,7 +100,6 @@ extern struct dram_timing_info dram_timing;
void ddr_load_train_firmware(enum fw_type type);
int ddr_init(struct dram_timing_info *timing_info);
int ddr_cfg_phy(struct dram_timing_info *timing_info);
void load_lpddr4_phy_pie(void);
void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num);
void *dram_config_save(struct dram_timing_info *info, unsigned long base);
void board_dram_ecc_scrub(void);
Expand Down Expand Up @@ -138,8 +134,8 @@ static inline void reg32setbit(unsigned long addr, u32 bit)
}

#define dwc_ddrphy_apb_wr(addr, data) \
reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data)
reg32_write(DDR_PHY_BASE + ddrphy_addr_remap(addr), data)
#define dwc_ddrphy_apb_rd(addr) \
reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr))
reg32_read(DDR_PHY_BASE + ddrphy_addr_remap(addr))

#endif
8 changes: 4 additions & 4 deletions drivers/ddr/imx/imx8m/ddr_init.c
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Original file line number Diff line number Diff line change
Expand Up @@ -168,13 +168,13 @@ void get_trained_CDD(u32 fsp)
ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
if (ddr_type == 0x20) {
for (i = 0; i < 6; i++) {
tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54013 + i) * 4);
tmp = reg32_read(DDR_PHY_BASE + (0x54013 + i) * 4);
cdd_cha[i * 2] = tmp & 0xff;
cdd_cha[i * 2 + 1] = (tmp >> 8) & 0xff;
}

for (i = 0; i < 7; i++) {
tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x5402c + i) * 4);
tmp = reg32_read(DDR_PHY_BASE + (0x5402c + i) * 4);
if (i == 0) {
cdd_cha[0] = (tmp >> 8) & 0xff;
} else if (i == 6) {
Expand Down Expand Up @@ -205,7 +205,7 @@ void get_trained_CDD(u32 fsp)
unsigned int ddr4_cdd[64];

for (i = 0; i < 29; i++) {
tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4);
tmp = reg32_read(DDR_PHY_BASE + (0x54012 + i) * 4);
ddr4_cdd[i * 2] = tmp & 0xff;
ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff;
}
Expand Down Expand Up @@ -401,7 +401,7 @@ int ddr_init(struct dram_timing_info *dram_timing)
* calibrating. Wait Calibrating done.
*/
do {
tmp = reg32_read(DDRPHY_CalBusy(0));
tmp = reg32_read(DDRPHY_CalBusy);
} while ((tmp & 0x1));

debug("DDRINFO:ddrphy calibration done\n");
Expand Down
15 changes: 7 additions & 8 deletions drivers/ddr/imx/phy/ddrphy_utils.c
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Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
Expand All @@ -6,7 +6,6 @@
#include <errno.h>
#include <log.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/sys_proto.h>
Expand All @@ -16,21 +15,21 @@
unsigned int reg;

do {
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004));
reg = reg32_read(DDR_PHY_BASE + ddrphy_addr_remap(0xd0004));
} while (reg & 0x1);
}

static inline void ack_pmu_message_receive(void)
{
unsigned int reg;

reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x0);
reg32_write(DDR_PHY_BASE + ddrphy_addr_remap(0xd0031), 0x0);

do {
reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0004));
reg = reg32_read(DDR_PHY_BASE + ddrphy_addr_remap(0xd0004));
} while (!(reg & 0x1));

reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0031), 0x1);
reg32_write(DDR_PHY_BASE + ddrphy_addr_remap(0xd0031), 0x1);
}

static inline unsigned int get_mail(void)
Expand All @@ -39,7 +38,7 @@

poll_pmu_message_ready();

reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032));
reg = reg32_read(DDR_PHY_BASE + ddrphy_addr_remap(0xd0032));

ack_pmu_message_receive();

Expand All @@ -52,9 +51,9 @@

poll_pmu_message_ready();

reg = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0032));
reg = reg32_read(DDR_PHY_BASE + ddrphy_addr_remap(0xd0032));

reg2 = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(0xd0034));
reg2 = reg32_read(DDR_PHY_BASE + ddrphy_addr_remap(0xd0034));

reg2 = (reg2 << 16) | reg;

Expand Down
3 changes: 1 addition & 2 deletions drivers/ddr/imx/phy/helper.c
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,6 @@
#include <errno.h>
#include <asm/io.h>
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#include <asm/arch/ddr.h>
#include <asm/arch/ddr.h>
#include <asm/sections.h>

DECLARE_GLOBAL_DATA_PTR;
Expand All @@ -22,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR;

#define IMEM_OFFSET_ADDR 0x00050000
#define DMEM_OFFSET_ADDR 0x00054000
#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
#define DDR_TRAIN_CODE_BASE_ADDR DDR_PHY_BASE

binman_sym_declare(ulong, ddr_1d_imem_fw, image_pos);
binman_sym_declare(ulong, ddr_1d_imem_fw, size);
Expand Down