arch/stm32f0l0g0: add watchdog support

Documentation/platforms/arm/stm32c0/index.rst

@@ -35,8 +35,8 @@ CRC         No
 ADC         Yes
 TIM         Yes
 IRTIM       No
-IWDG        No
-WWDG        No
+IWDG        Yes
+WWDG        Yes
 I2C         Yes
 USART       Yes
 SPI         Yes

Documentation/platforms/arm/stm32f0/index.rst

@@ -40,8 +40,8 @@ COMP        No
 TSC         No
 TIM         Yes
 IRTIM       No
-IWDG        No
-WWDG        No
+IWDG        Yes
+WWDG        Yes
 RTC         No
 I2C         Yes
 USART       Yes

Documentation/platforms/arm/stm32g0/index.rst

@@ -39,8 +39,8 @@ AES         Yes
 TIM         Yes
 LPTIM       No
 IRTIM       No
-IWDG        No
-WWDG        No
+IWDG        Yes
+WWDG        Yes
 RTC         No
 TAMP        No
 I2C         Yes

Documentation/platforms/arm/stm32l0/index.rst

@@ -34,8 +34,8 @@ AES         Yes
 RNG         Yes
 TIM         Yes
 LPTIM       No
-IWDG        No
-WWDG        No
+IWDG        Yes
+WWDG        Yes
 RTC         No
 I2C         Yes
 USART       Yes

arch/arm/src/stm32f0l0g0/CMakeLists.txt

@@ -31,6 +31,7 @@ list(
   stm32_irq.c
   stm32_lowputc.c
   stm32_serial.c
+  stm32_lsi.c
   stm32_rcc.c)
 
 if(CONFIG_STM32F0L0G0_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK)
@@ -101,4 +102,12 @@ if(CONFIG_STM32F0L0G0_TIM)
   list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c)
 endif()
 
+if(CONFIG_STM32F0L0G0_IWDG)
+  list(APPEND SRCS stm32_iwdg.c)
+endif()
+
+if(CONFIG_STM32F0L0G0_WWDG)
+  list(APPEND SRCS stm32_wwdg.c)
+endif()
+
 target_sources(arch PRIVATE ${SRCS})

arch/arm/src/stm32f0l0g0/Make.defs

@@ -23,7 +23,7 @@
 include armv6-m/Make.defs
 
 CHIP_CSRCS  = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c
-CHIP_CSRCS += stm32_lowputc.c stm32_serial.c stm32_rcc.c
+CHIP_CSRCS += stm32_lowputc.c stm32_serial.c stm32_rcc.c stm32_lsi.c
 
 ifneq ($(CONFIG_STM32F0L0G0_RTC_LSECLOCK)$(CONFIG_STM32F0L0G0_LCD_LSECLOCK),)
 CHIP_CSRCS += stm32_lse.c
@@ -92,3 +92,11 @@ endif
 ifeq ($(CONFIG_STM32F0L0G0_TIM),y)
 CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c
 endif
+
+ifeq ($(CONFIG_STM32F0L0G0_IWDG),y)
+CHIP_CSRCS += stm32_iwdg.c
+endif
+
+ifeq ($(CONFIG_STM32F0L0G0_WWDG),y)
+CHIP_CSRCS += stm32_wwdg.c
+endif

arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h

@@ -0,0 +1,80 @@
+/****************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32_DBGMCU_IDCODE       0x40015800  /* MCU identifier */
+#define STM32_DBGMCU_CR           0x40015804  /* MCU debug */
+#define STM32_DBGMCU_APB1_FZ      0x40015808  /* Debug MCU APB1 freeze register */
+#define STM32_DBGMCU_APB2_FZ      0x4001580c  /* Debug MCU APB2 freeze register */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* MCU identifier */
+
+#define DBGMCU_IDCODE_DEVID_SHIFT (0)       /* Bits 11-0: Device Identifier */
+#define DBGMCU_IDCODE_DEVID_MASK  (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
+#define DBGMCU_IDCODE_REVID_SHIFT (16)      /* Bits 31-16:  Revision Identifier */
+#define DBGMCU_IDCODE_REVID_MASK  (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
+
+/* MCU debug */
+
+#define DBGMCU_CR_SLEEP           (1 << 0)  /* Bit 0: Debug Sleep Mode */
+#define DBGMCU_CR_STOP            (1 << 1)  /* Bit 1: Debug Stop Mode */
+#define DBGMCU_CR_STANDBY         (1 << 2)  /* Bit 2: Debug Standby mode */
+
+/* Debug MCU APB freeze register 1 */
+
+#ifdef CONFIG_ARCH_CHIP_STM32C0
+#  define DBGMCU_APB1_TIM2STOP    (1 << 0)   /* Bit 0: TIM2 stopped when core is halted */
+#  define DBGMCU_APB1_TIM3STOP    (1 << 1)   /* Bit 1: TIM3 stopped when core is halted */
+#  define DBGMCU_APB1_RTCSTOP     (1 << 10)  /* Bit 10: RTC stopped when core is halted */
+#  define DBGMCU_APB1_WWDGSTOP    (1 << 11)  /* Bit 11: WWDG stopped when core is halted */
+#  define DBGMCU_APB1_IWDGSTOP    (1 << 12)  /* Bit 12: IWDG stopped when core is halted */
+#  define DBGMCU_APB1_I2C1STOP    (1 << 21)  /* Bit 21: SMBUS timeout mode stopped when Core is halted  */
+#endif
+
+/* Debug MCU APB freeze register 2 */
+
+#ifdef CONFIG_ARCH_CHIP_STM32C0
+#  define DBGMCU_APB1_TIM1STOP    (1 << 11)   /* Bit 1: TIM1 stopped when core is halted */
+#  define DBGMCU_APB1_TIM14STOP   (1 << 15)   /* Bit 15: TIM14 stopped when core is halted */
+#  define DBGMCU_APB1_TIM15STOP   (1 << 16)   /* Bit 16: TIM15 stopped when core is halted */
+#  define DBGMCU_APB1_TIM16STOP   (1 << 17)   /* Bit 16: TIM16 stopped when core is halted */
+#  define DBGMCU_APB1_TIM17STOP   (1 << 18)   /* Bit 16: TIM17 stopped when core is halted */
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H */

arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h

@@ -0,0 +1,141 @@
+/****************************************************************************
+ * arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H
+#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Offsets *********************************************************/
+
+#define STM32_IWDG_KR_OFFSET     0x0000  /* Key register (32-bit) */
+#define STM32_IWDG_PR_OFFSET     0x0004  /* Prescaler register (32-bit) */
+#define STM32_IWDG_RLR_OFFSET    0x0008  /* Reload register (32-bit) */
+#define STM32_IWDG_SR_OFFSET     0x000c  /* Status register (32-bit) */
+#define STM32_IWDG_WINR_OFFSET   0x000c  /* Window register (32-bit) */
+
+#define STM32_WWDG_CR_OFFSET     0x0000  /* Control Register (32-bit) */
+#define STM32_WWDG_CFR_OFFSET    0x0004  /* Configuration register (32-bit) */
+#define STM32_WWDG_SR_OFFSET     0x0008  /* Status register (32-bit) */
+
+/* Register Addresses *******************************************************/
+
+#define STM32_IWDG_KR            (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET)
+#define STM32_IWDG_PR            (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET)
+#define STM32_IWDG_RLR           (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET)
+#define STM32_IWDG_SR            (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET)
+#define STM32_IWDG_WINR          (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET)
+
+#define STM32_WWDG_CR            (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET)
+#define STM32_WWDG_CFR           (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET)
+#define STM32_WWDG_SR            (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET)
+
+/* Register Bitfield Definitions ********************************************/
+
+/* Key register (32-bit) */
+
+#define IWDG_KR_KEY_SHIFT        (0)       /* Bits 15-0: Key value (write only, read 0000h) */
+#define IWDG_KR_KEY_MASK         (0xffff << IWDG_KR_KEY_SHIFT)
+
+#define IWDG_KR_KEY_ENABLE       (0x5555)  /* Enable register access */
+#define IWDG_KR_KEY_DISABLE      (0x0000)  /* Disable register access */
+#define IWDG_KR_KEY_RELOAD       (0xaaaa)  /* Reload the counter */
+#define IWDG_KR_KEY_START        (0xcccc)  /* Start the watchdog */
+
+/* Prescaler register (32-bit) */
+
+#define IWDG_PR_SHIFT            (0)       /* Bits 2-0: Prescaler divider */
+#define IWDG_PR_MASK             (7 << IWDG_PR_SHIFT)
+#  define IWDG_PR_DIV4           (0 << IWDG_PR_SHIFT) /* 000: divider /4 */
+#  define IWDG_PR_DIV8           (1 << IWDG_PR_SHIFT) /* 001: divider /8 */
+#  define IWDG_PR_DIV16          (2 << IWDG_PR_SHIFT) /* 010: divider /16 */
+#  define IWDG_PR_DIV32          (3 << IWDG_PR_SHIFT) /* 011: divider /32 */
+#  define IWDG_PR_DIV64          (4 << IWDG_PR_SHIFT) /* 100: divider /64 */
+#  define IWDG_PR_DIV128         (5 << IWDG_PR_SHIFT) /* 101: divider /128 */
+#  define IWDG_PR_DIV256         (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */
+
+/* Reload register (32-bit) */
+
+#define IWDG_RLR_RL_SHIFT        (0)       /* Bits11:0 RL[11:0]: Watchdog counter reload value */
+#define IWDG_RLR_RL_MASK         (0x0fff << IWDG_RLR_RL_SHIFT)
+
+#define IWDG_RLR_MAX             (0xfff)
+
+/* Status register (32-bit) */
+
+#define IWDG_SR_PVU              (1 << 0)  /* Bit 0: Watchdog prescaler value update */
+#define IWDG_SR_RVU              (1 << 1)  /* Bit 1: Watchdog counter reload value update */
+#define IWDG_SR_WVU              (1 << 2)  /* Bit 2:  */
+
+/* Window register (32-bit) */
+
+#define IWDG_WINR_SHIFT          (0)
+#define IWDG_WINR_MASK           (0x0fff << IWDG_WINR_SHIFT)
+
+/* Control Register (32-bit) */
+
+#define WWDG_CR_T_SHIFT          (0)       /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */
+#define WWDG_CR_T_MASK           (0x7f << WWDG_CR_T_SHIFT)
+#  define WWDG_CR_T_MAX          (0x3f << WWDG_CR_T_SHIFT)
+#  define WWDG_CR_T_RESET        (0x40 << WWDG_CR_T_SHIFT)
+#define WWDG_CR_WDGA             (1 << 7)  /* Bit 7: Activation bit */
+
+/* Configuration register (32-bit) */
+
+#define WWDG_CFR_W_SHIFT         (0)       /* Bits 6:0 W[6:0] 7-bit window value */
+#define WWDG_CFR_W_MASK          (0x7f << WWDG_CFR_W_SHIFT)
+#define WWDG_CFR_WDGTB_SHIFT     (7)       /* Bits 8:7 [1:0]: Timer Base */
+#define WWDG_CFR_WDGTB_MASK      (3 << WWDG_CFR_WDGTB_SHIFT)
+#  define WWDG_CFR_PCLK1         (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
+#  define WWDG_CFR_PCLK1d2       (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
+#  define WWDG_CFR_PCLK1d4       (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
+#  define WWDG_CFR_PCLK1d8       (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
+
+#define WWDG_CFR_EWI             (1 << 9)  /* Bit 9: Early Wakeup Interrupt */
+
+/* Status register (32-bit) */
+
+#define WWDG_SR_EWIF             (1 << 0)  /* Bit 0: Early Wakeup Interrupt Flag */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */

arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h

@@ -34,6 +34,8 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+#undef HAVE_PWR_DBP /* No Disable backup write protection bit */
+
 /* Register Offsets *********************************************************/
 
 #define STM32_PWR_CR1_OFFSET   0x0000  /* Power control register 1 */
@@ -100,17 +102,9 @@
 #  define PWR_CR1_LPMS_STANDBY   (3 << PWR_CR1_LPMS_SHIFT) /* 011: Standby mode */
 #  define PWR_CR1_LPMS_SHUTDOWN  (4 << PWR_CR1_LPMS_SHIFT) /* 1xx: Shutdown mode */
 
-#define PWR_CR1_FPDSTOP          (1 << 3) /* Bit 3: Flash memory powered down during Stop mode */
                                           /* Bit 4: Reserved */
 #define PWR_CR1_FPDLPSLP         (1 << 5) /* Bit 5: Flash memory powered down during Low-power sleep mode */
                                           /* Bits 6-31: Reserved */
-#define PWR_CR1_DBP              (1 << 8) /* Bit 8: Disable Backup domain write protection */
-#define PWR_CR1_VOS_SHIFT        (9)      /* Bits 9-10: Voltage scaling range selection */
-#define PWR_CR1_VOS_MASK         (3 << PWR_CR1_VOS_SHIFT)
-#  define PWR_CR1_VOS_RANGE1     (1 << PWR_CR1_VOS_SHIFT) /* 01: Range 1 */
-#  define PWR_CR1_VOS_RANGE2     (2 << PWR_CR1_VOS_SHIFT) /* 10: Range 2 */
-
-#define PWR_CR1_LPR              (1 << 14) /* Bit 14: Low-power run */
 
 /* Power control register 2 */
 

arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h

@@ -34,6 +34,7 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+#define HAVE_PWR_DBP         1
 #undef HAVE_PWR_WKUP2
 #undef HAVE_PWR_WKUP3
 

arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h

@@ -34,6 +34,8 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+#define HAVE_PWR_DBP           1
+
 /* Register Offsets *********************************************************/
 
 #define STM32_PWR_CR1_OFFSET   0x0000  /* Power control register 1 */

arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h

@@ -36,6 +36,7 @@
 
 #define HAVE_PWR_WKUP2         1
 #define HAVE_PWR_WKUP3         1
+#define HAVE_PWR_DBP           1
 
 /* Register Offsets *********************************************************/