Ci flwadd by tommydcjung · Pull Request #514 · bespoke-silicon-group/bsg_manycore

tommydcjung · 2021-04-22T18:26:16Z

No description provided.

* Move wormhole concentrator outside pod ruche array * merge north and south vcaches traffic extend cid to 2-bit

* clean up branch trace * remote interrupt interface * npc_r * add mret encoding * fcsr load goes to rs2_val * interrupt csr test * add mcsr * interrupt trace test * set pc_init_val by _start; * interrupt remote test * remote interrrupt icache miss * trace interrupt icache miss test * CR * change remote interrupt eva * interrupt trace countdown * printing interrupt taken * interrupt trace float * mret display; debug_p * more test; remote interrupt ptr * interrupt trace jump loop * interrupt trace jump loop icache * interrupt dual source * interrupt trace branch loop icache * interrupt_trace_branch_mispredict_loop * remote load loop with interrupt

* io rtr tag client * set width_p for io rtr tag clients

* wh return fiof * fix

* Added reset_done port to dpi interface * Adds missing inputs to endpoint_to_fifos * Removed pod x/y * Adds CUDA kernel for DMA test * Adds missing file Co-authored-by: Dustin Richmond <dustinar@uw.edu>

* temp commit * fix regression * offset dmem start addr by 8 bytes for interrupt handler * CR * cr * adding .dmem.interrupt section; declaring _interrupt_arr in crt.S; update hello to use interrupt arr using extern * add comment

* Adding trace interrupt test for idiv, fdiv and imul * Adding remote interrupt tests with multiplier and divider * Testing multiple remote interrupts, icache misses in handler and different handler return strategies * Adding a interrupt test regression * Deleting duplicates within the interrupt regression suite without contaminating author history * Using a macro for the start code * Makefile cleanup * More regression makefile cleanup * Modifying macro name * Adding npc mret test * Deleting duplicate files and noting original author in specific files * Adding interrupt tests to the no recurse list * Adding a mini threading test * Directed test exposing the need for PR #463 * Adding a readme * Minor makefile modifications * Adding missing test to regression

* Rewrite Victim Cache Profiler Parser (#428) * Fixed vcache profiler bugs with re-write * fix tile parser to get correct min cycle no. for absolute total cycles calculation when using multiple tags (#480) * Fix header_print_p (for bigblade) Bugs: * Order of operations: Python binds or higher than > * Counting of repeated tags. Previously, only the last tag was counted * Iteration-order aware tag window New Features: * Atomic Misses * Response Stalls * More documentation * Remove deprecated code * Small field name modifications * Fixed issue with mismatched tags error * Fixed issue where TG origin/dim were confused for Device origin/dim Co-authored-by: Emily Furst <eafurst@cs.washington.edu>

* imul mux order * fp_exe flush minimize toggles * add comment * add comment 2

refactor dram hash func

* io rtr * pod row refactor * move bsg_tag out of pod * remove unused port * clean up * move out wh ruche buffers * move out west ruche buffers

* num_clk_ports_p for subarray * fix x -> c * fix * add param in pod row

tommydcjung · 2021-04-22T18:34:08Z

https://github.com/taylor-bsg/pulp-riscv-gcc/blame/master/gcc/config/riscv/riscv.md#L3663

taylor-bsg · 2021-04-22T18:35:22Z

+//  Machine Format:
+//          rs1   rs2       rd    opcode
+//  0000000_?????_?????_111_?????_0000100
+`define RV32_FLWADD_OP 7'b0000100


// Pulpino supports a post-increment instruction in their compiler
// here: https://github.com/taylor-bsg/pulp-riscv-gcc/blame/master/gcc/config/riscv/riscv.md#L3663
// this can be used as a reference for adding compiler support
// for instructions with sideeffects to addresses.

taylor-bsg · 2021-04-22T18:35:43Z

  // Load & Store
-  logic is_load_op;       // Op loads data from memory
-  logic is_store_op;      // Op stores data to memory
+  logic is_load_op;       // Op is lw or flw


should now add flwadd?

taylor-bsg · 2021-04-22T18:38:04Z

+        | (instruction_i.funct7 == `RV32_FCVT_S_F2I_FUN7)); // FCVT.W.S, FCVT.WU.S
+    end
+    `RV32_FLWADD_OP: begin
+      decode_o.write_rd = (instruction_i.funct7 == 7'b0000000) & (instruction_i.funct3 == 3'b111) & (instruction_i.rs1 != '0);


presumably part of this redundant with the fact that we are in the RW32_FLWADD_OP case statement?

Probably can just add FLWADD_OP to standard set of cases at the top of the casez statement?

taylor-bsg · 2021-04-22T18:38:31Z

+      decode_o.write_rd = (instruction_i.funct7 == 7'b0000000) & (instruction_i.funct3 == 3'b111) & (instruction_i.rs1 != '0);
+    end
+    `RV32_SYSTEM: begin
+      decode_o.write_rd = (instruction_i.rd != '0); // CSRRW, CSRRS


combine with case above?

taylor-bsg · 2021-04-22T18:39:43Z

    `RV32_BRANCH, `RV32_STORE, `RV32_OP: begin
      decode_o.read_rs2 = 1'b1;
    end
+    `RV32_FLWADD_OP: begin


combine with above?

taylor-bsg · 2021-04-22T18:40:59Z

+      decode_o.read_frs2 = 1'b0;
+      decode_o.read_frs3 = 1'b0;
+      decode_o.write_frd = 1'b1;
+      decode_o.is_fp_op = 1'b0;


comment why FLWADD is not an fp op

taylor-bsg · 2021-04-22T18:41:24Z

  assign dmem_v_o = is_local_dmem_addr &
    (exe_decode_i.is_load_op | exe_decode_i.is_store_op |
-     exe_decode_i.is_lr_op | exe_decode_i.is_lr_aq_op);
+     exe_decode_i.is_lr_op | exe_decode_i.is_lr_aq_op | exe_decode_i.is_flwadd_op);


now is_load_op includes is_flwadd_op right?

taylor-bsg · 2021-04-22T18:41:37Z


  assign remote_req_v_o = icache_miss_i |
-    ((exe_decode_i.is_load_op | exe_decode_i.is_store_op | exe_decode_i.is_amo_op) & ~is_local_dmem_addr);
+    ((exe_decode_i.is_load_op | exe_decode_i.is_store_op | exe_decode_i.is_amo_op | exe_decode_i.is_flwadd_op) & ~is_local_dmem_addr);


same comment as above?

taylor-bsg · 2021-04-22T18:43:46Z

+  // is_flwadd_op has exe_r.decode.write_rd high will not trigger int_remote_load_in_exe
  wire int_remote_load_in_exe = remote_req_in_exe & exe_r.decode.is_load_op & exe_r.decode.write_rd;
-  wire float_remote_load_in_exe = remote_req_in_exe & exe_r.decode.is_load_op & exe_r.decode.write_frd;
+  wire float_remote_load_in_exe = remote_req_in_exe & (exe_r.decode.is_load_op | exe_r.decode.is_flwadd_op) & exe_r.decode.write_frd;


is_load_op now includes is_flwadd_op?

wire int_remote_load_in_exe = remote_req_in_exe & exe_r.decode.is_load_op & ~exe_r.decode.is_flwadd_op & exe_r.decode.write_rd;

taylor-bsg · 2021-04-22T18:49:01Z

+    |(id_r.decode.read_frs2 & (id_rs2 == exe_r.instruction.rd) & exe_r.decode.write_frd)
+    |(id_r.decode.read_frs3 & (id_rs3 == exe_r.instruction.rd) & exe_r.decode.write_frd));
+



seems like the above is redundant if we include flwadd in local_load_in_exe

taylor-bsg

High level feed back: the code is simpler if is_load includes flwadd; (which is currently the case, but the code does not reflect this)

tommydcjung and others added 30 commits January 11, 2021 15:21

bigblade

452932a

multipod spmd support

a7357de

global_pod_ptr test

9fe856a

remove south io router row

dc92ab8

include right side ruche buffer inside the pod

c54aa8c

bsg_tag interface on pods

dbf3be9

fix bug

65159ee

override bsg_pod x y

03a140f

fix branch_rv32

1b22d35

Minor fix to bsg_manycore_hor_io_router filter

ffb8616

Tieing off unnecessary ruche link ports on io router (#456)

d11ef58

simplify remote resp force logic

8ab692e

typo

4fc8116

Move wormhole concentrator outside pod ruche array (#457)

af10ab7

* Move wormhole concentrator outside pod ruche array * merge north and south vcaches traffic extend cid to 2-bit

prevent updating npc_r while in interrupt; add debugging pc signals

7225afa

bsg_manycore_endpoint_standard use e_remote_sw

0debc61

use packet_lo.reg_id for e_remote_sw

9f56876

io rtr tag client (#461)

1c5b2fd

* io rtr tag client * set width_p for io rtr tag clients

fix sw handling (#462)

1aceb6b

reduce tag payload for wh_dest_cord (#465)

0e31ab8

Bigblade wh return fifo (#467)

9e2dc33

* wh return fiof * fix

Reset done dpi (#466)

fd75efb

* Added reset_done port to dpi interface * Adds missing inputs to endpoint_to_fifos * Removed pod x/y * Adds CUDA kernel for DMA test * Adds missing file Co-authored-by: Dustin Richmond <dustinar@uw.edu>

Bigblade dmem addr shift (#459)

8ded807

* temp commit * fix regression * offset dmem start addr by 8 bytes for interrupt handler * CR * cr * adding .dmem.interrupt section; declaring _interrupt_arr in crt.S; update hello to use interrupt arr using extern * add comment

use mutex for coremark ee_printf.c

1224feb

split wh traffic (#471)

cebe024

fix sp to 4KB-4

0496018

npc mret (#463)

c78197e

CI interrupt

268e537

tommydcjung and others added 16 commits March 30, 2021 08:12

remove 4x4 hbm2 (#502)

baea7ff

refactor dram hash func

a6a995d

add comment about address format

3f4b5a1

imul mux order (#500)

82b52ef

* imul mux order * fp_exe flush minimize toggles * add comment * add comment 2

Merge pull request #505 from bespoke-silicon-group/ci_dram_hash

6066b5e

refactor dram hash func

Ci pod refactor (#499)

6cace26

* io rtr * pod row refactor * move bsg_tag out of pod * remove unused port * clean up * move out wh ruche buffers * move out west ruche buffers

Update Makefile.llvminstall (#506)

f984cc6

surround hetero type stuff so dc doesn't crash (#508)

9081216

Ci num clk ports (#509)

567a984

* num_clk_ports_p for subarray * fix x -> c * fix * add param in pod row

fix ruche connection on the east row edge (#510)

3acb35f

flwadd

43f78e7

comments

09af7aa

move flwadd to flw opcode space

9a4d722

forwarding logic fix

ea733cc

tests

f21a590

tommydcjung added the Work In Progress label Apr 22, 2021

taylor-bsg reviewed Apr 22, 2021

View reviewed changes

tommydcjung force-pushed the ci_bigblade branch from 499d31e to 89419da Compare July 2, 2021 17:32

		\|(id_r.decode.read_frs2 & (id_rs2 == exe_r.instruction.rd) & exe_r.decode.write_frd)
		\|(id_r.decode.read_frs3 & (id_rs3 == exe_r.instruction.rd) & exe_r.decode.write_frd));

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tommydcjung commented Apr 22, 2021

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