Fix verification generation for event driven simulators

[andrewb1999]

Event driven simulators (such as vivado xsim and synopsys vcs) behave fundamentally differently than cycle based simulators like icarus and verilator. Rather than taking a full cycle step at a time, individual values within a cycle can be updated independently of each other, which makes the current way of combinationally checking disjoint guards invalid. We can fix this issue by only performing disjoint checks at the positive edge of the clock, which is fine because it's the only time that we truly care about the guards being disjoint. Without these fixes you have to turn off verification to run calyx verilog through commercial simulators.

[rachitnigam]

Thanks for the changes @andrewb1999! There are two failing tests. Could you please update them to retrigger the build?

[rachitnigam]

Once the change is working, let's merge it!