Assertion cleanup - not using clock edges or resets to check and disable assertion

[clayton8]

Many of your assertions are continuously being monitored instead of checking on posedge of clock and disabling on negedge of clock. For example:

https://github.com/chipsalliance/Cores-VeeR-EL2/blob/main/design/lsu/el2_lsu_stbuf.sv#L344
https://github.com/chipsalliance/Cores-VeeR-EL2/blob/main/design/el2_dma_ctrl.sv#L505

In addition you seem to be disabling assertions at time 0 and the reenable them to avoid them firing at time 0:

https://github.com/chipsalliance/Cores-VeeR-EL2/blob/main/design/el2_veer_wrapper.sv#L965C1-L969C6

This isn't good practice and will not work if we add sync reset support #429.

Please:

1. Change all assertions to use "assert property (@(posedge clk) disable iff(!rst_l)"
2. Remove the time 0 assertoff/on in el2_veer_wrapper.sv

[kgugala]

This is something @clayton8. @moidx and @kgugala agreed to hold off for now, this can be done as part of #430 when we want to land that sync resets.