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Merged
alaindargelas merged 2 commits into from
Mar 2, 2026
Merged

wire type #4075

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682bd74
wire type
alaindargelas Mar 2, 2026
98ffd45
wire type
alaindargelas Mar 2, 2026
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8 changes: 8 additions & 0 deletions include/Surelog/Design/Signal.h
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Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,10 @@ class Signal final {
void setModPort(ModPort* modport) { m_modPort = modport; }
void setDirection(VObjectType direction) { m_direction = direction; }
void setType(VObjectType type) { m_type = type; }
// For typed net declarations (e.g. "wand integer"), stores the original net
// keyword (paNetType_Wand/Wor/Wire) separate from the data type in m_type.
VObjectType getSubNetType() const { return m_subNetType; }
void setSubNetType(VObjectType t) { m_subNetType = t; }
void setDataType(const DataType* dtype) { m_dataType = dtype; }
void setPackedDimension(NodeId id) { m_packedDimension = id; }
void setUnpackedDimension(NodeId id) { m_unpackedDimension = id; }
Expand Down Expand Up @@ -116,6 +120,10 @@ class Signal final {
const FileContent* m_fileContent = nullptr;
NodeId m_nodeId;
VObjectType m_type = VObjectType::slNoType;
// Preserved original net keyword for typed net declarations (e.g., "wand integer").
// When set, m_type holds the data type (e.g., paIntegerAtomType_Integer) and
// m_subNetType holds the net keyword (e.g., paNetType_Wand).
VObjectType m_subNetType = VObjectType::slNoType;
VObjectType m_direction = VObjectType::slNoType;
ModuleDefinition* m_interfaceDef = nullptr;
ModPort* m_modPort = nullptr;
Expand Down
6 changes: 6 additions & 0 deletions src/DesignCompile/CompileHelper.cpp
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Expand Up @@ -2187,6 +2187,9 @@ bool CompileHelper::compileNetDeclaration(DesignComponent* component,
sig->setTypespecId(NetType);
sig->attributes(attributes);
if (isSigned) sig->setSigned();
// Preserve the original net keyword (e.g. wand/wor) for typed net decls
// like "wand typename". ElaborationStep may later overwrite m_type.
if (subnettype != VObjectType::slNoType) sig->setSubNetType(subnettype);
component->getSignals().push_back(sig);
} else {
Signal* sig =
Expand All @@ -2197,6 +2200,9 @@ bool CompileHelper::compileNetDeclaration(DesignComponent* component,
sig->setStatic();
sig->attributes(attributes);
if (isSigned) sig->setSigned();
// Preserve the original net keyword (e.g. wand/wor) for typed net decls
// like "wand integer" where nettype was overwritten by the data type.
if (subnettype != VObjectType::slNoType) sig->setSubNetType(subnettype);
component->getSignals().push_back(sig);
}

Expand Down
33 changes: 21 additions & 12 deletions src/DesignCompile/NetlistElaboration.cpp
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Expand Up @@ -1838,6 +1838,10 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
// Nets pass
const DataType* dtype = sig->getDataType();
VObjectType subnettype = sig->getType();
// For typed net declarations (e.g. "wand integer"), the original net keyword
// (paNetType_Wand/Wor/Wire) is preserved in getSubNetType(). The m_type
// (subnettype) holds the data type which may have overridden the net keyword.
VObjectType netKeyword = sig->getSubNetType();
UHDM::typespec* tps = nullptr;
// Determine if the "signal" is a net or a var
bool isNet = true;
Expand Down Expand Up @@ -1868,6 +1872,11 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
isNet = true;
}
}
// Typed net declarations like "wand integer" or "wand typename" store the
// original net keyword in getSubNetType(). Override isNet for these cases.
if (netKeyword != VObjectType::slNoType) {
isNet = true;
}

NodeId typeSpecId = sig->getTypeSpecId();
if (typeSpecId) {
Expand Down Expand Up @@ -1990,7 +1999,7 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
for (auto a : *sig->attributes()) a->VpiParent(logicn);
}
logicn->VpiSigned(sig->isSigned());
logicn->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
logicn->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
// Move range to typespec for simple types
// logicn->Ranges(packedDimensions);
ref_typespec* rt = s.MakeRef_typespec();
Expand Down Expand Up @@ -2106,9 +2115,9 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
stv->VpiParent(pnets);
for (auto r : *packedDimensions) r->VpiParent(pnets);
obj = pnets;
pnets->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
pnets->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
} else {
stv->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
stv->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
}
} else if (const Struct* st = datatype_cast<const Struct*>(dtype)) {
struct_net* stv = s.MakeStruct_net();
Expand All @@ -2130,9 +2139,9 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
stv->VpiParent(pnets);
for (auto r : *packedDimensions) r->VpiParent(pnets);
obj = pnets;
pnets->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
pnets->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
} else {
stv->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
stv->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
}
} else if (dtype->getCategory() == DataType::Category::PARAMETER ||
dtype->getCategory() == DataType::Category::SIMPLE_TYPEDEF) {
Expand All @@ -2154,7 +2163,7 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
for (auto a : *sig->attributes()) a->VpiParent(logicn);
}
logicn->VpiSigned(sig->isSigned());
logicn->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
logicn->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
// Move range to typespec for simple types
// logicn->Ranges(packedDimensions);
ref_typespec* rt = s.MakeRef_typespec();
Expand Down Expand Up @@ -2185,9 +2194,9 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
stv->VpiParent(pnets);
for (auto r : *packedDimensions) r->VpiParent(pnets);
obj = pnets;
pnets->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
pnets->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
} else {
stv->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
stv->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
}
} else if (spec->UhdmType() == uhdmenum_typespec) {
enum_net* stv = s.MakeEnum_net();
Expand All @@ -2210,9 +2219,9 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
stv->VpiParent(pnets);
for (auto r : *packedDimensions) r->VpiParent(pnets);
obj = pnets;
pnets->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
pnets->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
} else {
stv->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
stv->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
}
} else if (spec->UhdmType() == uhdmbit_typespec) {
bit_var* logicn = s.MakeBit_var();
Expand Down Expand Up @@ -2265,7 +2274,7 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
for (auto a : *sig->attributes()) a->VpiParent(logicn);
}
logicn->VpiSigned(sig->isSigned());
logicn->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
logicn->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
ref_typespec* rt = s.MakeRef_typespec();
rt->VpiParent(logicn);
rt->Actual_typespec(tps);
Expand Down Expand Up @@ -2370,7 +2379,7 @@ bool NetlistElaboration::elabSignal(Signal* sig, ModuleInstance* instance,
} else {
logic_net* logicn = s.MakeLogic_net();
logicn->VpiSigned(sig->isSigned());
logicn->VpiNetType(UhdmWriter::getVpiNetType(sig->getType()));
logicn->VpiNetType(UhdmWriter::getVpiNetType(netKeyword != VObjectType::slNoType ? netKeyword : sig->getType()));
if (sig->attributes()) {
logicn->Attributes(sig->attributes());
for (auto a : *sig->attributes()) a->VpiParent(logicn);
Expand Down
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