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grammar: accept hierarchical_identifier as bind target#4089

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alaindargelas merged 1 commit into
chipsalliance:masterfrom
alainmarcel:bind_hier_path
May 29, 2026
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grammar: accept hierarchical_identifier as bind target#4089
alaindargelas merged 1 commit into
chipsalliance:masterfrom
alainmarcel:bind_hier_path

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The bind_directive rule only matched bind <identifier> ... — bind to a module type. IEEE 1800-2017 §23.11 also allows the second form, bind bind_target_instance bind_instantiation, where the target is a hierarchical_identifier with an optional bit-select (e.g. bind $root.top.foo_i bar bound_i (.*) or
bind top.foo_i bar bound_i (.*)). Surelog rejected these with "no viable alternative at input 'bind $root'".

Extend bind_directive to accept either a hierarchical_identifier (form 2) or an identifier with an optional :-prefixed instance list (form 1). The two alternatives are LL(1)-distinguishable because hierarchical_identifier requires at least one .identifier after the first identifier (or the $root. prefix), so a bare identifier still goes through the form-1 path.

Adds tests/BindHierPath/ covering the $root.top.foo_i form (sourced from yosys/tests/bind/hier.sv).

The bind_directive rule only matched `bind <identifier> ...` — bind
to a module type.  IEEE 1800-2017 §23.11 also allows the second
form, `bind bind_target_instance bind_instantiation`, where the
target is a hierarchical_identifier with an optional bit-select
(e.g. `bind $root.top.foo_i bar bound_i (.*)` or
`bind top.foo_i bar bound_i (.*)`).  Surelog rejected these with
"no viable alternative at input 'bind \$root'".

Extend bind_directive to accept either a hierarchical_identifier
(form 2) or an identifier with an optional `:`-prefixed instance
list (form 1).  The two alternatives are LL(1)-distinguishable
because hierarchical_identifier requires at least one `.identifier`
after the first identifier (or the `$root.` prefix), so a bare
identifier still goes through the form-1 path.

Adds tests/BindHierPath/ covering the `$root.top.foo_i` form
(sourced from yosys/tests/bind/hier.sv).
@alaindargelas alaindargelas merged commit a8949a6 into chipsalliance:master May 29, 2026
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