Skip to content
This repository was archived by the owner on Jun 3, 2024. It is now read-only.

Conversation

@kamilrakoczy
Copy link
Collaborator

This PR adds test with different types of multirange bit-select/part-select.

It is used to test support for multiranges with uhdm-plugin and upstream yosys.
Signed-off-by: Kamil Rakoczy krakoczy@antmicro.com

@kamilrakoczy kamilrakoczy marked this pull request as draft October 29, 2021 13:34
);
//logic [7:0] [31:0] rdata_d, rdata_q;
logic [7:0] a, b, c;
logic [7:0] d_array[0:3];

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
When an unpacked dimension range is zero-based ([0:N-1]), declare size as [N] instead. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]

//logic [7:0] [31:0] rdata_d, rdata_q;
logic [7:0] a, b, c;
logic [7:0] d_array[0:3];
logic [7:0] e_array[3:0];

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]

logic [7:0] d_array[0:3];
logic [7:0] e_array[3:0];

logic [7:0] mult_array_a[3:0][3:0];

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]

logic [7:0] d_array[0:3];
logic [7:0] e_array[3:0];

logic [7:0] mult_array_a[3:0][3:0];

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]

logic [7:0] e_array[3:0];

logic [7:0] mult_array_a[3:0][3:0];
logic [7:0] mult_array_b[3:0][3:0];

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]

logic [7:0] mult_array_c[3:0][3:0];
logic [7:0] mult_array_d[3:0][3:0];

logic packed_mult_array_a[3:0][3:0];

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]

logic [7:0] mult_array_c[3:0][3:0];
logic [7:0] mult_array_d[3:0][3:0];

logic packed_mult_array_a[3:0][3:0];

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]

logic [7:0] mult_array_d[3:0][3:0];

logic packed_mult_array_a[3:0][3:0];
logic packed_mult_array_b[3:0][3:0];

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]

logic [7:0] mult_array_d[3:0][3:0];

logic packed_mult_array_a[3:0][3:0];
logic packed_mult_array_b[3:0][3:0];

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]


end

endmodule

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
assign f_array[1] = 8'hE;
assign g_array = f_array;

if (1'b1 == 1'b1) begin : test
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
All generate block labels must start with g_ or gen_ [Style: generate-constructs] [generate-label-prefix]

Sign up for free to subscribe to this conversation on GitHub. Already have an account? Sign in.

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant