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@RRozak RRozak commented Feb 24, 2022

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Signed-off-by: Ryszard Różak <rrozak@antmicro.com>
} my_union_t;

initial begin
my_union_t un [9:0];

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Unpacked dimension range must be declared in big-endian ([0:N-1]) order. Declare zero-based big-endian unpacked dimensions sized as [N]. [Style: unpacked-ordering] [unpacked-dimensions-range-ordering]

Signed-off-by: Ryszard Różak <rrozak@antmicro.com>
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RRozak commented Mar 3, 2022

Unpacked unions are unsupported by both verilators and both yosys. It's better to wait with the merge until there will be at least one tool that can be tested on it

@@ -0,0 +1,12 @@
module top1(output logic [3:0] o);

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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Declared module does not match the first dot-delimited component of file name: "top" [Style: file-names] [module-filename]

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