Skip to content
This repository was archived by the owner on Jun 3, 2024. It is now read-only.

Conversation

@rkapuscik
Copy link
Contributor

No description provided.

@@ -0,0 +1,3 @@
module dut (output int o);
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Declared module does not match the first dot-delimited component of file name: "dut2" [Style: file-names] [module-filename]

@@ -0,0 +1,3 @@
module dut (output int o);
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Declared module does not match the first dot-delimited component of file name: "dut1" [Style: file-names] [module-filename]

Signed-off-by: Rafal Kapuscik <rkapuscik@antmicro.com>
Sign up for free to subscribe to this conversation on GitHub. Already have an account? Sign in.

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant