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Add IncludeTwice test #686

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@@ -0,0 +1,3 @@
module dut (output int o);
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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Declared module does not match the first dot-delimited component of file name: "dut2" [Style: file-names] [module-filename]

@@ -0,0 +1,3 @@
module dut (output int o);
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⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Declared module does not match the first dot-delimited component of file name: "dut1" [Style: file-names] [module-filename]

Signed-off-by: Rafal Kapuscik <[email protected]>
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