Skip to content
This repository was archived by the owner on Jun 3, 2024. It is now read-only.
Open
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 2 additions & 0 deletions tests/AssignLocalParamStaticFunction/Makefile.in
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
TOP_FILE := $(TEST_DIR)/top.sv
TOP_MODULE := top
36 changes: 36 additions & 0 deletions tests/AssignLocalParamStaticFunction/main.cpp
Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
#include <iostream>
#include <verilated_vcd_c.h>

#define VL_DEBUG
#include "Vtop.h"
#include "verilated.h"

static vluint64_t main_time = 0;

double
sc_time_stamp()
{
return main_time;
}

int main (int argc, char **argv) {
Verilated::commandArgs(argc, argv);
Vtop *top = new Vtop();

Verilated::traceEverOn(true);
VerilatedVcdC* tfp = new VerilatedVcdC;
top->trace(tfp, 99);
tfp->open("dump.vcd");

while (!Verilated::gotFinish() && (main_time < 100)) {
top->eval();
tfp->dump(main_time);

main_time += 1;
}
top->final();
tfp->close();
delete top;

return 0;
}
22 changes: 22 additions & 0 deletions tests/AssignLocalParamStaticFunction/top.sv
Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
module top #(
)(
);
typedef int unsigned ASSIGN_VADDR_RET_T[2];
function static ASSIGN_VADDR_RET_T ASSIGN_VADDR();
for (int i = 0; i < 2; i++) begin
ASSIGN_VADDR[i] = 5;
end
endfunction

localparam int unsigned VADDR = ASSIGN_VADDR();
if (VADDR[0] != 5) begin
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
All generate block statements must have a label [Style: generate-statements] [generate-label]

$fatal(1,"--[0] should be 5 ");
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

end;
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

if (VADDR[1] != 5) begin
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
All generate block statements must have a label [Style: generate-statements] [generate-label]

$fatal(1,"--[1] should be 5");
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

end;
Copy link

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

⚠️ [verible-verilog-lint] reported by reviewdog 🐶
Use spaces, not tabs. [Style: tabs] [no-tabs]

endmodule

module main;
top #() top1;
endmodule
6 changes: 6 additions & 0 deletions tests/AssignLocalParamStaticFunction/yosys_script.tcl
Original file line number Diff line number Diff line change
@@ -0,0 +1,6 @@
source ../yosys_common.tcl

prep -top \\top
write_verilog
write_verilog yosys.sv
sim -rstlen 10 -vcd dump.vcd