Variable length message feature

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-532ce69a5733cecb3cfab2c48093dafdb6e263fbd2168fd533b027fa127a803e93a8c760e364fdfc05cdb7094bbe38f8
+a167996774a6fa24a26689a741f9ebc3c3e6d3696f7f044c1d41960a226845b126f046ede20da9284920e27abba1df90

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1741299077
+1745607697

docs/AdamsBridgeHardwareSpecification.md

@@ -59,6 +59,9 @@ The ML-DSA-87 architecture inputs and outputs are described in the fol
 | message                     | Input           | Sign/Verify     | 64            |
 | verification result         | Output          | Verify          | 64            |
 | External_Mu                 | Input           | Sign/Verify     | 64            |
+| message strobe              | Input           | Sign/Verify     | 1             |
+| ctx size                    | Input           | Sign/Verify     | 1             |
+| ctx                         | Input           | Sign/Verify     | 255 (+1)      |
 | pk                          | Input/Output    | Keygen/Verify   | 2592          |
 | signature                   | Input/Output    | Sign/Verify     | 4627 (+1)     |
 | sk\_out (software only)     | Output          | Keygen          | 4896          |
@@ -81,7 +84,8 @@ The ML-DSA-87 architecture inputs and outputs are described in the fol
 
 | Bits     | Identifier  | Access | Reset | Decoded | Name |
 | :------- | :---------- | :----- | :---- | :------ | :--- |
-| \[31:6\] | \-          | \-     | \-    |         | \-   |
+| \[31:7\] | \-          | \-     | \-    |         | \-   |
+| \[6\]    | STREAM_MSG  | w      | 0x0   |         | \-   |
 | \[5\]    | EXTERNAL_MU | w      | 0x0   |         | \-   |
 | \[4\]    | PCR_SIGN    | w      | 0x0   |         | \-   |
 | \[3\]    | ZEROIZE     | w      | 0x0   |         | \-   |
@@ -122,18 +126,27 @@ Run PCR Signing flow: Run MLDSA KeyGen+Signing flow to sign PCRs.
 
 ### EXTERNAL_MU 
 
-Enable ExternalMu Mode.
-(this mode is hard turned off for now.)
+Enable External_Mu Mode. (this mode is hard turned off for now.)
+The External_mu variant of ML-DSA modifies the standard signing and verifying process by allowing the precomputed mu to be externally provided instead of being internally derived from the message and public key. In this variant, the signing procedure accepts mu as an explicit input, making it suitable for environments where mu is generated offline for efficiency. While the core signing and verifying algorithm remains unchanged, the message input register is ignored in this mode.
+
+### STREAM_MSG 
+
+Enable streaming message mode.
+In this mode, the controller will wait when reaching the point that it requires the message data, and asserts the MSG_STREAM_READY bit in the status register.
+Once MSG_STREAM_READY is asserted, the user can stream the message, one dword at a time, by writing to dword 0 of the message register.
+For the last dword, the user must set the MSG_STROBE register to appropriately indicate the valid bytes. 
+If a message is dword aligned, a value of 0x0 must be written to the MSG_STROBE register to indicate the last dword. 
 
 ## status 
 
 ​The read-only status register consists of the following flags: 
 
 | Bits     | Identifier | Access | Reset | Decoded | Name |
 | :------- | :--------- | :----- | :---- | :------ | :--- |
-| \[31:2\] | \-         | \-     | \-    |         | \-   |
-| \[1\]    | VALID      | r      | 0x0   |         | \-   |
-| \[0\]    | READY      | r      | 0x0   |         | \-   |
+| \[31:3\] | \-                | \-     | \-    |         | \-   |
+| \[2\]    | MSG_STREAM_READY  | r      | 0x0   |         | \-   |
+| \[1\]    | VALID             | r      | 0x0   |         | \-   |
+| \[0\]    | READY             | r      | 0x0   |         | \-   |
 
 ### READY 
 
@@ -143,6 +156,10 @@ Enable ExternalMu Mode.
 
 ​Indicates if the process is computed and the output is valid. 
 
+### MSG_STREAM_READY
+
+​Indicates if the core is ready to process the message.
+
 ## entropy
 
 Entropy is required for SCA countermeasures to randomize the inputs with no change in the outputs. The entropy can be any 512-bit value in \[0 : 2^512-1\]. 
@@ -162,13 +179,27 @@ This register is used to support both deterministic and hedge variants of ML-DSA
 
 ## message
 
-This architecture supports PureML-DSA defined by NIST with an empty ctx.
-However, the current architecture only supports the message size of 512 bits. This restrection will be removed
+When not in streaming message mode, this architecture supports PureML-DSA defined by NIST with an empty ctx.
+When streaming message mode is enabled, this field is ignored except for dword 0 which is used to stream in the message.
 
 ## verification result
 
 To mitigate a possible fault attack on Boolean flag verification result, a 64-byte register is considered. Firmware is responsible for comparing the computed result with a certain segment of signature (segment c\~), and if they are equal the signature is valid.
 
+## msg strobe
+
+A 4-bit indication of enabled bytes in the next dword of the streamed message.
+Resets to a value of 0xF indicating all bytes are valid. Any non 0xF value will be treated as the last dword of the message.
+Dword aligned messages should have a write of 0x0 to msg strobe to indicate the message is done being streamed.
+
+## ctx size
+
+A 8-bit indication of the size in bytes of the ctx to be used.
+
+## ctx
+
+This register stores the ctx field. It is applied only during streaming message mode.
+
 ## sk\_out
 
 This register stores the private key for keygen if seed is given by software. This register is read by ML-DSA user, i.e., software, after keygen operation.

src/abr_libs/config/abr_libs.vf

@@ -14,6 +14,7 @@ ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_msg_buffer.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv
@@ -24,10 +25,10 @@ ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv
-${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv

src/abr_libs/config/compile.yml

@@ -18,6 +18,7 @@ targets:
       - $COMPILE_ROOT/rtl/abr_piso_4.sv
       - $COMPILE_ROOT/rtl/abr_piso.sv
       - $COMPILE_ROOT/rtl/abr_sample_buffer.sv
+      - $COMPILE_ROOT/rtl/abr_msg_buffer.sv
       - $COMPILE_ROOT/rtl/abr_ahb_defines_pkg.sv
       - $COMPILE_ROOT/rtl/abr_ahb_slv_sif.sv
       - $COMPILE_ROOT/rtl/abr_masked_AND.sv
@@ -47,6 +48,7 @@ targets:
       - $COMPILE_ROOT/rtl/abr_piso_4.sv
       - $COMPILE_ROOT/rtl/abr_piso.sv
       - $COMPILE_ROOT/rtl/abr_sample_buffer.sv
+      - $COMPILE_ROOT/rtl/abr_msg_buffer.sv
       - $COMPILE_ROOT/rtl/abr_ahb_defines_pkg.sv
       - $COMPILE_ROOT/rtl/abr_ahb_slv_sif.sv
       - $COMPILE_ROOT/rtl/abr_masked_AND.sv

src/abr_libs/config/masking_tb.vf

@@ -1,10 +1,5 @@
-+incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/tb
 +incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl
-${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_A2B_conv_tb.sv
-${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_N_bit_Boolean_adder_tb.sv
-${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_B2A_conv_tb.sv
-${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_N_bit_mult_tb.sv
-${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_N_bit_mult_two_share_tb.sv
++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/tb
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv
@@ -15,4 +10,9 @@ ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv
-${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_A2B_conv_tb.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_N_bit_Boolean_adder_tb.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_B2A_conv_tb.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_N_bit_mult_tb.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/tb/abr_masked_N_bit_mult_two_share_tb.sv

src/abr_libs/rtl/abr_msg_buffer.sv

@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// MSG Buffer takes in NUM_WR samples and valid bits
+// Valid samples are assumed contiguous and shifted onto a buffer
+// Outputs are presented valid once NUM_RD entries are valid in the buffer
+
+module abr_msg_buffer
+  //    import ::*;
+  #(
+   parameter NUM_WR = 5
+  ,parameter NUM_RD  = 4
+  ,parameter BUFFER_DATA_W = 32
+  ,localparam BUFFER_DEPTH = (NUM_WR + NUM_RD)
+  ,localparam BUF_W = BUFFER_DEPTH*BUFFER_DATA_W
+  )
+  (
+  input logic clk,
+  input logic rst_b,
+
+  input logic flush,
+
+  //input data
+  input  logic [NUM_WR-1:0]                    data_valid_i,
+  input  logic [NUM_WR-1:0][BUFFER_DATA_W-1:0] data_i,
+  output logic                                 buffer_full_o,
+  //output data
+  output logic [NUM_RD-1:0]                    data_valid_o,
+  input  logic                                 data_hold_i,
+  output logic [NUM_RD-1:0][BUFFER_DATA_W-1:0] data_o
+
+  );
+
+  logic buffer_rd, buffer_wr;
+  logic update_buffer;
+
+  //Incoming samples to write to buffer
+  logic [BUFFER_DEPTH-1:0][BUFFER_DATA_W-1:0] buffer_wr_data, buffer_wr_data_shift;
+  logic [BUFFER_DEPTH-1:0] buffer_wr_valid, buffer_wr_valid_shift;
+
+  //Valid sample buffer
+  logic [BUFFER_DEPTH-1:0] buffer_valid, buffer_valid_d, buffer_valid_shift;
+  logic [BUFFER_DEPTH-1:0][BUFFER_DATA_W-1:0] buffer, buffer_d, buffer_shift;
+  logic [$clog2(BUFFER_DEPTH):0] num_valid;
+
+
+  //Buffer is full when it can't take a full write cycle
+  //Check for at least N entries available, where N is the difference between WR/RD bandwidth
+  generate
+    if (NUM_WR <= NUM_RD) always_comb buffer_full_o = buffer_valid[BUFFER_DEPTH-NUM_WR] & ~buffer_rd;
+    else                  always_comb buffer_full_o = buffer_rd ? buffer_valid[(BUFFER_DEPTH-(NUM_WR-NUM_RD))] :
+                                                      buffer_valid[BUFFER_DEPTH-NUM_WR];
+  endgenerate
+  //Read when we have NUM_RD worth of valid data
+  //Flush will pop any remaining entries
+  always_comb buffer_rd = ~data_hold_i & (buffer_valid[NUM_RD-1] | (flush & buffer_valid[0])); 
+  //Write as long as we have 1 valid sample and not full
+  always_comb buffer_wr = (|data_valid_i) & ~buffer_full_o;
+  //update buffer for any read or write
+  always_comb update_buffer = buffer_rd | buffer_wr;
+
+  always_comb begin
+    //count the valid entries in the buffer already
+    num_valid = '0;
+    for (int i = 0; i < BUFFER_DEPTH; i++) begin
+      if (buffer_valid[i] == 1'b1) num_valid += 1'b1;
+    end
+  end
+
+  always_comb begin
+    buffer_wr_data = '0;
+    buffer_wr_valid = '0;
+    for (int sample = 0; sample < NUM_WR; sample++) begin
+      buffer_wr_data[sample] = data_valid_i[sample] ? data_i[sample][BUFFER_DATA_W-1:0] : '0;
+      buffer_wr_valid[sample] = data_valid_i[sample];
+    end
+  end
+
+  always_comb begin
+    //shift the write data left by the count, or count - NUM_RD if there is a read
+    buffer_wr_data_shift = buffer_rd ? buffer_wr_data << (num_valid - NUM_RD)*BUFFER_DATA_W : 
+                                       buffer_wr_data << (num_valid)*BUFFER_DATA_W;
+    buffer_wr_valid_shift = buffer_wr ?
+                            (buffer_rd ? buffer_wr_valid << (num_valid - NUM_RD) :
+                                         buffer_wr_valid << (num_valid)) : '0;
+  end
+
+  //Shift the buffer contents and append new samples
+  always_comb begin
+    //shift the buffer data right by NUM_RD if there is a read
+    buffer_shift = buffer_rd ? BUF_W'(buffer >> (NUM_RD*BUFFER_DATA_W)) : buffer;
+    buffer_valid_shift = buffer_rd ? BUFFER_DEPTH'(buffer_valid >> NUM_RD) : buffer_valid;
+
+    //OR together the write data and the buffer data
+    buffer_d = buffer_shift | buffer_wr_data_shift;
+    buffer_valid_d = buffer_valid_shift | buffer_wr_valid_shift;
+  end
+
+  always_ff @(posedge clk or negedge rst_b) begin
+    if (!rst_b) begin
+      buffer <= '0;
+      buffer_valid <= '0;
+    end else if (update_buffer) begin
+      buffer <= buffer_d;
+      buffer_valid <= buffer_valid_d;
+    end 
+  end
+
+  //Set output valid bits
+  always_comb data_valid_o = buffer_valid[NUM_RD-1:0];
+  always_comb data_o = buffer[NUM_RD-1:0];
+
+  `ABR_ASSERT(ERR_INV_STROBE, data_valid_i inside {4'b0000, 4'b0001, 4'b0011, 4'b0111, 4'b1111}, clk, !rst_b)
+
+endmodule

src/abr_prim/config/abr_prim.vf

@@ -39,4 +39,5 @@ ${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_fifo_sync.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_arbiter_ppc.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sum_tree.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_subreg_ext.sv
-${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_edge_detector.sv
+${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_edge_detector.sv
+${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv

src/abr_sha3/config/abr_sha3.vf

@@ -1,8 +1,9 @@
++incdir+${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl
 +incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl
 +incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl
 +incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl
-+incdir+${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl
 +incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl
+${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh
 ${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv
@@ -17,6 +18,7 @@ ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_msg_buffer.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv
@@ -27,6 +29,7 @@ ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv
@@ -39,8 +42,6 @@ ${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cipher_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv
-${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3_pkg.sv
-${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv
@@ -77,4 +78,5 @@ ${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_edge_detector.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_round.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_2share.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3pad.sv
-${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3.sv
+${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3.sv
+${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv

src/abr_sha3/config/abr_sha3_tb.vf

@@ -1,14 +1,15 @@
 +incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl
 +incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl
++incdir+${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl
 +incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl
 +incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl
-+incdir+${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl
 +incdir+${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl
 +incdir+${ADAMSBRIDGE_ROOT}/src/abr_sha3/tb
 ${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh
 ${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/mldsa_sampler_top/rtl/mldsa_sampler_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv
@@ -20,6 +21,7 @@ ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_msg_buffer.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv
@@ -30,6 +32,7 @@ ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv
@@ -42,8 +45,6 @@ ${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_mubi_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_cipher_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_pkg.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv
-${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3_pkg.sv
-${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop_en.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_flop.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_prim_generic/rtl/abr_prim_generic_buf.sv
@@ -82,4 +83,5 @@ ${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_keccak_2share.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3pad.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_sha3/rtl/abr_sha3.sv
 ${ADAMSBRIDGE_ROOT}/src/abr_sha3/tb/abr_sha3_tb_pkg.sv
-${ADAMSBRIDGE_ROOT}/src/abr_sha3/tb/abr_sha3_tb.sv
+${ADAMSBRIDGE_ROOT}/src/abr_sha3/tb/abr_sha3_tb.sv
+${ADAMSBRIDGE_ROOT}/src/abr_prim/rtl/abr_prim_sparse_fsm_pkg.sv