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kgugalakgugala
committed
Switch to use DCLS VeeR version
Signed-off-by: Karol Gugala <[email protected]>
1 parent a7ce171 commit 107d4a9

13 files changed

+87
-10
lines changed

‎src/integration/config/caliptra_top_tb.vf

+3-1
Original file line numberDiff line numberDiff line change
@@ -218,6 +218,7 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv
218218
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_lib.sv
219219
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/mem_lib.sv
220220
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv
221+
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_regfile_if.sv
221222
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv
222223
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv
223224
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv
@@ -234,6 +235,7 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv
234235
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv
235236
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pmp.sv
236237
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv
238+
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_lockstep.sv
237239
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
238240
${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv
239241
${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv
@@ -621,4 +623,4 @@ ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_block_encrypt.sv
621623
${CALIPTRA_ROOT}/src/csrng/rtl/csrng_state_db.sv
622624
${CALIPTRA_ROOT}/src/csrng/rtl/csrng_cmd_stage.sv
623625
${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv
624-
${CALIPTRA_ROOT}/src/integration/rtl/caliptra_top.sv
626+
${CALIPTRA_ROOT}/src/integration/rtl/caliptra_top.sv

‎src/integration/rtl/caliptra_top.sv

+15
Original file line numberDiff line numberDiff line change
@@ -439,6 +439,12 @@ always_comb begin
439439
el2_icache_stub.ic_tag_data_raw_pre = '0;
440440
end
441441

442+
logic cptra_panic;
443+
444+
`ifndef RV_LOCKSTEP_ENABLE
445+
assign cptra_panic = 1'b0;
446+
`endif
447+
442448
el2_veer_wrapper rvtop (
443449
`ifdef CALIPTRA_FORCE_CPU_RESET
444450
.rst_l ( 1'b0 ),
@@ -577,6 +583,13 @@ el2_veer_wrapper rvtop (
577583
// Caliptra Memory Export Interface
578584
.el2_mem_export (el2_mem_export),
579585

586+
`ifdef RV_LOCKSTEP_ENABLE
587+
// Shadow Core control
588+
.disable_corruption_detection_i(1'b0),
589+
.lockstep_err_injection_en_i(1'b0),
590+
.corruption_detected_o(cptra_panic),
591+
`endif
592+
580593
.core_id ('0),
581594
.scan_mode ( scan_mode ), // To enable scan mode
582595
.mbist_mode ( 1'b0 ) // to enable mbist
@@ -1359,6 +1372,8 @@ soc_ifc_top1
13591372
.fw_update_rst_window(fw_update_rst_window),
13601373
//multiple cryptos operating at once, assert fatal error
13611374
.crypto_error(crypto_error),
1375+
// DCLS error
1376+
.dcls_error (cptra_panic ),
13621377
//caliptra uncore jtag ports
13631378
.cptra_uncore_dmi_reg_en( cptra_uncore_dmi_reg_en ),
13641379
.cptra_uncore_dmi_reg_wr_en( cptra_uncore_dmi_reg_wr_en ),

‎src/integration/rtl/config_defines.svh

+1
Original file line numberDiff line numberDiff line change
@@ -100,6 +100,7 @@
100100
`define CALIPTRA_RV_TOP `CALIPTRA_TOP.caliptra_top_dut
101101

102102
`define RV_TOP `CALIPTRA_RV_TOP.rvtop
103+
`define RV_LOCKSTEP_ENABLE 1
103104

104105
`define CALIPTRA_ICG cptra_clk_gate
105106

‎src/riscv_core/veer_el2/config/compile.yml

+2
Original file line numberDiff line numberDiff line change
@@ -54,6 +54,7 @@ targets:
5454
- $COMPILE_ROOT/rtl/lib/el2_lib.sv
5555
- $COMPILE_ROOT/rtl/lib/mem_lib.sv
5656
- $COMPILE_ROOT/rtl/lib/el2_mem_if.sv
57+
- $COMPILE_ROOT/rtl/lib/el2_regfile_if.sv
5758
- $COMPILE_ROOT/rtl/lsu/el2_lsu_addrcheck.sv
5859
- $COMPILE_ROOT/rtl/lsu/el2_lsu_bus_buffer.sv
5960
- $COMPILE_ROOT/rtl/lsu/el2_lsu_bus_intf.sv
@@ -70,6 +71,7 @@ targets:
7071
- $COMPILE_ROOT/rtl/el2_pic_ctrl.sv
7172
- $COMPILE_ROOT/rtl/el2_pmp.sv
7273
- $COMPILE_ROOT/rtl/el2_veer.sv
74+
- $COMPILE_ROOT/rtl/el2_veer_lockstep.sv
7375
- $COMPILE_ROOT/rtl/el2_veer_wrapper.sv
7476
tops: [el2_veer_wrapper]
7577
rtl_lint:

‎src/riscv_core/veer_el2/config/el2_veer_wrapper.vf

+3-1
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv
3333
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_lib.sv
3434
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/mem_lib.sv
3535
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv
36+
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_el2_regfile_if.sv
3637
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv
3738
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv
3839
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv
@@ -49,4 +50,5 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv
4950
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv
5051
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pmp.sv
5152
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv
52-
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
53+
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_lockstep.sv
54+
${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv

‎src/riscv_core/veer_el2/rtl/common_defines.sv

+3
Original file line numberDiff line numberDiff line change
@@ -244,6 +244,9 @@
244244
`define RV_INST_ACCESS_MASK5 'hffffffff
245245
`define RV_INST_ACCESS_MASK6 'hffffffff
246246
`define RV_INST_ACCESS_MASK7 'hffffffff
247+
`define RV_LOCKSTEP_DELAY 3
248+
`define RV_LOCKSTEP_ENABLE 1
249+
`define RV_LOCKSTEP_REGFILE_ENABLE 1
247250
`define RV_PMP_ENTRIES 64
248251
`define REGWIDTH 32
249252
`define RV_RESET_VEC 'h00000000

‎src/riscv_core/veer_el2/rtl/el2_param.vh

+3
Original file line numberDiff line numberDiff line change
@@ -167,6 +167,9 @@ parameter el2_param_t pt = '{
167167
INST_ACCESS_MASK6 : 36'h0FFFFFFFF ,
168168
INST_ACCESS_MASK7 : 36'h0FFFFFFFF ,
169169
LOAD_TO_USE_PLUS1 : 5'h00 ,
170+
LOCKSTEP_DELAY : 7'h03 ,
171+
LOCKSTEP_ENABLE : 5'h01 ,
172+
LOCKSTEP_REGFILE_ENABLE : 5'h01 ,
170173
LSU2DMA : 5'h00 ,
171174
LSU_BUS_ID : 5'h01 ,
172175
LSU_BUS_PRTY : 6'h02 ,

‎src/riscv_core/veer_el2/rtl/el2_pdef.vh

+3
Original file line numberDiff line numberDiff line change
@@ -168,6 +168,9 @@ typedef struct packed {
168168
logic [35:0] INST_ACCESS_MASK6;
169169
logic [35:0] INST_ACCESS_MASK7;
170170
logic [4:0] LOAD_TO_USE_PLUS1;
171+
logic [6:0] LOCKSTEP_DELAY;
172+
logic [4:0] LOCKSTEP_ENABLE;
173+
logic [4:0] LOCKSTEP_REGFILE_ENABLE;
171174
logic [4:0] LSU2DMA;
172175
logic [4:0] LSU_BUS_ID;
173176
logic [5:0] LSU_BUS_PRTY;

‎src/soc_ifc/rtl/soc_ifc_external_reg.rdl

+2-1
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,8 @@ reg {
2828
rw_rw_sticky_hw dccm_ecc_unc=0; /* Uncorrectable double-bit error in DCCM */
2929
rw_rw_sticky_hw nmi_pin=0; /* Non-Maskable Interrupt due to WDT timeout */
3030
rw_rw_sticky_hw crypto_err=0; /* Crypto parallel operation error No Mask */
31-
field {sw=r; hw=w;} rsvd[28]=28'h0;
31+
rw_rw_sticky_hw dcls_error=0; /* Non-Maskable DCLS error */
32+
field {sw=r; hw=w;} rsvd[27]=27'h0;
3233
} CPTRA_HW_ERROR_FATAL;
3334
reg {
3435
name = "Hardware Error Non-Fatal";

‎src/soc_ifc/rtl/soc_ifc_reg.sv

+33-1
Original file line numberDiff line numberDiff line change
@@ -415,6 +415,10 @@ module soc_ifc_reg (
415415
logic next;
416416
logic load_next;
417417
} crypto_err;
418+
struct packed{
419+
logic next;
420+
logic load_next;
421+
} dcls_error;
418422
} CPTRA_HW_ERROR_FATAL;
419423
struct packed{
420424
struct packed{
@@ -1505,6 +1509,9 @@ module soc_ifc_reg (
15051509
struct packed{
15061510
logic value;
15071511
} crypto_err;
1512+
struct packed{
1513+
logic value;
1514+
} dcls_error;
15081515
} CPTRA_HW_ERROR_FATAL;
15091516
struct packed{
15101517
struct packed{
@@ -2428,6 +2435,30 @@ module soc_ifc_reg (
24282435
end
24292436
end
24302437
assign hwif_out.CPTRA_HW_ERROR_FATAL.crypto_err.value = field_storage.CPTRA_HW_ERROR_FATAL.crypto_err.value;
2438+
// Field: soc_ifc_reg.CPTRA_HW_ERROR_FATAL.dcls_error
2439+
always_comb begin
2440+
automatic logic [0:0] next_c;
2441+
automatic logic load_next_c;
2442+
next_c = field_storage.CPTRA_HW_ERROR_FATAL.dcls_error.value;
2443+
load_next_c = '0;
2444+
if(decoded_reg_strb.CPTRA_HW_ERROR_FATAL && decoded_req_is_wr) begin // SW write 1 clear
2445+
next_c = field_storage.CPTRA_HW_ERROR_FATAL.dcls_error.value & ~(decoded_wr_data[4:4] & decoded_wr_biten[4:4]);
2446+
load_next_c = '1;
2447+
end else if(hwif_in.CPTRA_HW_ERROR_FATAL.dcls_error.we) begin // HW Write - we
2448+
next_c = hwif_in.CPTRA_HW_ERROR_FATAL.dcls_error.next;
2449+
load_next_c = '1;
2450+
end
2451+
field_combo.CPTRA_HW_ERROR_FATAL.dcls_error.next = next_c;
2452+
field_combo.CPTRA_HW_ERROR_FATAL.dcls_error.load_next = load_next_c;
2453+
end
2454+
always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
2455+
if(~hwif_in.cptra_pwrgood) begin
2456+
field_storage.CPTRA_HW_ERROR_FATAL.dcls_error.value <= 1'h0;
2457+
end else if(field_combo.CPTRA_HW_ERROR_FATAL.dcls_error.load_next) begin
2458+
field_storage.CPTRA_HW_ERROR_FATAL.dcls_error.value <= field_combo.CPTRA_HW_ERROR_FATAL.dcls_error.next;
2459+
end
2460+
end
2461+
assign hwif_out.CPTRA_HW_ERROR_FATAL.dcls_error.value = field_storage.CPTRA_HW_ERROR_FATAL.dcls_error.value;
24312462
// Field: soc_ifc_reg.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock
24322463
always_comb begin
24332464
automatic logic [0:0] next_c;
@@ -7046,7 +7077,8 @@ module soc_ifc_reg (
70467077
assign readback_array[0][1:1] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value : '0;
70477078
assign readback_array[0][2:2] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value : '0;
70487079
assign readback_array[0][3:3] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.crypto_err.value : '0;
7049-
assign readback_array[0][31:4] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_ERROR_FATAL.rsvd.next : '0;
7080+
assign readback_array[0][4:4] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.dcls_error.value : '0;
7081+
assign readback_array[0][31:5] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_ERROR_FATAL.rsvd.next : '0;
70507082
assign readback_array[1][0:0] = (decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value : '0;
70517083
assign readback_array[1][1:1] = (decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value : '0;
70527084
assign readback_array[1][2:2] = (decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value : '0;

‎src/soc_ifc/rtl/soc_ifc_reg_pkg.sv

+3-1
Original file line numberDiff line numberDiff line change
@@ -12,14 +12,15 @@ package soc_ifc_reg_pkg;
1212
} soc_ifc_reg__rw_rw_sticky_hw__in_t;
1313

1414
typedef struct packed{
15-
logic [27:0] next;
15+
logic [26:0] next;
1616
} soc_ifc_reg__CPTRA_HW_ERROR_FATAL__rsvd__in_t;
1717

1818
typedef struct packed{
1919
soc_ifc_reg__rw_rw_sticky_hw__in_t iccm_ecc_unc;
2020
soc_ifc_reg__rw_rw_sticky_hw__in_t dccm_ecc_unc;
2121
soc_ifc_reg__rw_rw_sticky_hw__in_t nmi_pin;
2222
soc_ifc_reg__rw_rw_sticky_hw__in_t crypto_err;
23+
soc_ifc_reg__rw_rw_sticky_hw__in_t dcls_error;
2324
soc_ifc_reg__CPTRA_HW_ERROR_FATAL__rsvd__in_t rsvd;
2425
} soc_ifc_reg__CPTRA_HW_ERROR_FATAL__in_t;
2526

@@ -749,6 +750,7 @@ package soc_ifc_reg_pkg;
749750
soc_ifc_reg__rw_rw_sticky_hw__out_t dccm_ecc_unc;
750751
soc_ifc_reg__rw_rw_sticky_hw__out_t nmi_pin;
751752
soc_ifc_reg__rw_rw_sticky_hw__out_t crypto_err;
753+
soc_ifc_reg__rw_rw_sticky_hw__out_t dcls_error;
752754
} soc_ifc_reg__CPTRA_HW_ERROR_FATAL__out_t;
753755

754756
typedef struct packed{

‎src/soc_ifc/rtl/soc_ifc_reg_uvm.sv

+7-2
Original file line numberDiff line numberDiff line change
@@ -14,12 +14,14 @@ package soc_ifc_reg_uvm;
1414
soc_ifc_reg__CPTRA_HW_ERROR_FATAL_bit_cg dccm_ecc_unc_bit_cg[1];
1515
soc_ifc_reg__CPTRA_HW_ERROR_FATAL_bit_cg nmi_pin_bit_cg[1];
1616
soc_ifc_reg__CPTRA_HW_ERROR_FATAL_bit_cg crypto_err_bit_cg[1];
17-
soc_ifc_reg__CPTRA_HW_ERROR_FATAL_bit_cg rsvd_bit_cg[28];
17+
soc_ifc_reg__CPTRA_HW_ERROR_FATAL_bit_cg dcls_error_bit_cg[1];
18+
soc_ifc_reg__CPTRA_HW_ERROR_FATAL_bit_cg rsvd_bit_cg[27];
1819
soc_ifc_reg__CPTRA_HW_ERROR_FATAL_fld_cg fld_cg;
1920
rand uvm_reg_field iccm_ecc_unc;
2021
rand uvm_reg_field dccm_ecc_unc;
2122
rand uvm_reg_field nmi_pin;
2223
rand uvm_reg_field crypto_err;
24+
rand uvm_reg_field dcls_error;
2325
rand uvm_reg_field rsvd;
2426

2527
function new(string name = "soc_ifc_reg__CPTRA_HW_ERROR_FATAL");
@@ -40,13 +42,16 @@ package soc_ifc_reg_uvm;
4042
this.nmi_pin.configure(this, 1, 2, "W1C", 1, 'h0, 1, 1, 0);
4143
this.crypto_err = new("crypto_err");
4244
this.crypto_err.configure(this, 1, 3, "W1C", 1, 'h0, 1, 1, 0);
45+
this.dcls_error = new("dcls_error");
46+
this.dcls_error.configure(this, 1, 4, "W1C", 1, 'h0, 1, 1, 0);
4347
this.rsvd = new("rsvd");
44-
this.rsvd.configure(this, 28, 4, "RO", 1, 'h0, 1, 1, 0);
48+
this.rsvd.configure(this, 27, 5, "RO", 1, 'h0, 1, 1, 0);
4549
if (has_coverage(UVM_CVR_REG_BITS)) begin
4650
foreach(iccm_ecc_unc_bit_cg[bt]) iccm_ecc_unc_bit_cg[bt] = new();
4751
foreach(dccm_ecc_unc_bit_cg[bt]) dccm_ecc_unc_bit_cg[bt] = new();
4852
foreach(nmi_pin_bit_cg[bt]) nmi_pin_bit_cg[bt] = new();
4953
foreach(crypto_err_bit_cg[bt]) crypto_err_bit_cg[bt] = new();
54+
foreach(dcls_error_bit_cg[bt]) dcls_error_bit_cg[bt] = new();
5055
foreach(rsvd_bit_cg[bt]) rsvd_bit_cg[bt] = new();
5156
end
5257
if (has_coverage(UVM_CVR_FIELD_VALS))

‎src/soc_ifc/rtl/soc_ifc_top.sv

+9-3
Original file line numberDiff line numberDiff line change
@@ -154,6 +154,7 @@ module soc_ifc_top
154154
output logic fw_update_rst_window,
155155

156156
input logic crypto_error,
157+
input logic dcls_error,
157158

158159
//caliptra uncore jtag ports
159160
input logic cptra_uncore_dmi_reg_en,
@@ -1284,18 +1285,21 @@ wdt #(
12841285
// Also calculate whether or not an unmasked event is being set, so we can
12851286
// trigger the SOC interrupt signal
12861287
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.crypto_err .we = crypto_error;
1288+
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.dcls_error .we = dcls_error;
12871289
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.we = rv_ecc_sts.cptra_iccm_ecc_double_error & ~fw_update_rst_window;
12881290
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.we = rv_ecc_sts.cptra_dccm_ecc_double_error & ~fw_update_rst_window;
12891291
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.nmi_pin .we = nmi_intr;
12901292
// Using we+next instead of hwset allows us to encode the reserved fields in some fashion
12911293
// other than bit-hot in the future, if needed (e.g. we need to encode > 32 FATAL events)
12921294
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.crypto_err .next = 1'b1;
1295+
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.dcls_error .next = 1'b1;
12931296
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.next = 1'b1;
12941297
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.next = 1'b1;
12951298
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.nmi_pin .next = 1'b1;
1296-
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.rsvd.next[27:0] = 28'h0;
1299+
always_comb soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.rsvd.next[26:0] = 27'h0;
12971300
// Flag the write even if the field being written to is already set to 1 - this is a new occurrence of the error and should trigger a new interrupt
12981301
always_comb unmasked_hw_error_fatal_write = (soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.crypto_err .we && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.crypto_err .next) ||
1302+
(soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.dcls_error .we && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.dcls_error .next) ||
12991303
(soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.we && ~soc_ifc_reg_hwif_out.internal_hw_error_fatal_mask.mask_iccm_ecc_unc.value && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.iccm_ecc_unc.next) ||
13001304
(soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.we && ~soc_ifc_reg_hwif_out.internal_hw_error_fatal_mask.mask_dccm_ecc_unc.value && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.next) ||
13011305
(soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.nmi_pin .we && ~soc_ifc_reg_hwif_out.internal_hw_error_fatal_mask.mask_nmi_pin .value && |soc_ifc_reg_hwif_in.CPTRA_HW_ERROR_FATAL.nmi_pin .next);
@@ -1342,7 +1346,8 @@ always_comb cptra_uncore_dmi_locked_reg_rdata_in = ({32{(cptra_uncore_dmi_reg_ad
13421346
({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_FW_ERROR_ENC)}} & soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_ENC.error_code.value) |
13431347
({32{(cptra_uncore_dmi_reg_addr == DMI_REG_BOOTFSM_GO)}} & {31'b0, soc_ifc_reg_hwif_out.CPTRA_BOOTFSM_GO.GO.value}) |
13441348
({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_DBG_MANUF_SERVICE_REG)}} & soc_ifc_reg_hwif_out.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value) |
1345-
({32{(cptra_uncore_dmi_reg_addr == DMI_REG_HW_FATAL_ERROR)}} & {soc_ifc_reg_hwif_in .CPTRA_HW_ERROR_FATAL.rsvd.next[27:0],
1349+
({32{(cptra_uncore_dmi_reg_addr == DMI_REG_HW_FATAL_ERROR)}} & {soc_ifc_reg_hwif_in .CPTRA_HW_ERROR_FATAL.rsvd.next[26:0],
1350+
soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.dcls_error.value,
13461351
soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.crypto_err.value,
13471352
soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.nmi_pin.value,
13481353
soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value,
@@ -1377,7 +1382,8 @@ always_comb cptra_uncore_dmi_unlocked_reg_rdata_in = ({32{(cptra_uncore_dmi_reg_
13771382
({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_FW_ERROR_ENC)}} & soc_ifc_reg_hwif_out.CPTRA_FW_ERROR_ENC.error_code.value) |
13781383
({32{(cptra_uncore_dmi_reg_addr == DMI_REG_BOOTFSM_GO)}} & {31'b0, soc_ifc_reg_hwif_out.CPTRA_BOOTFSM_GO.GO.value}) |
13791384
({32{(cptra_uncore_dmi_reg_addr == DMI_REG_CPTRA_DBG_MANUF_SERVICE_REG)}} & soc_ifc_reg_hwif_out.CPTRA_DBG_MANUF_SERVICE_REG.DATA.value) |
1380-
({32{(cptra_uncore_dmi_reg_addr == DMI_REG_HW_FATAL_ERROR)}} & {soc_ifc_reg_hwif_in .CPTRA_HW_ERROR_FATAL.rsvd.next[27:0],
1385+
({32{(cptra_uncore_dmi_reg_addr == DMI_REG_HW_FATAL_ERROR)}} & {soc_ifc_reg_hwif_in .CPTRA_HW_ERROR_FATAL.rsvd.next[26:0],
1386+
soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.dcls_error.value,
13811387
soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.crypto_err.value,
13821388
soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.nmi_pin.value,
13831389
soc_ifc_reg_hwif_out.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value,

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