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Pull requests: chipsalliance/caliptra-rtl
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[DOC] Add connectivity requirements of trace ports and explain on-die osc requirement
#1165
opened Jan 7, 2026 by
calebofearth
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[DOC] Document JTAG register alias addresses and accessibility patch_v2.0
#1143
opened Dec 5, 2025 by
Nitsirks
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[DOC] Document JTAG register alias addresses and accessibility patch_v2.1
#1142
opened Dec 5, 2025 by
Nitsirks
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[DOC] Document JTAG register alias addresses and accessibility patch_v1.1
#1141
opened Dec 5, 2025 by
Nitsirks
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Caliptra RTL rdc constraints update and RDC version update
#1092
opened Oct 22, 2025 by
pjangid30
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[DOC] do not reset caliptra separately from the host controller
#1087
opened Oct 16, 2025 by
rob-tetrel
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[DOC] Remove 'definition of done' from integration requirements
#1061
opened Sep 29, 2025 by
calebofearth
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Brought out reset signals at the interface for necessary reset handline
#922
opened Jul 15, 2025 by
jchanga
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[UVM] Add AXI sub sequences to soc_ifc environment
#831
opened Mar 18, 2025 by
upadhyayulakiran
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Auto-generation of regression yaml files for Calitpra_top regression runs.
#755
opened Feb 25, 2025 by
anjpar
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Patch 1.0 RTL with Lint Fixes
enhancement
New feature or request
#518
opened May 17, 2024 by
calebofearth
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Fix PC setup after waking from clock gating in Verilator
Future
#380
opened Jan 16, 2024 by
robertszczepanski
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