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Pull requests: chipsalliance/caliptra-rtl

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Pull requests list

[doc] Revise and detail TRNG configuration for integration spec
#861 opened Apr 27, 2025 by moidx Loading…
2
Update ABR submodule to include streaming message and dword swizzle fix
#860 opened Apr 27, 2025 by Nitsirks Loading…
RDC and Synthesis documentation update
#858 opened Apr 23, 2025 by amullick007 Loading…
1
SHA3 Register Manual Release
#853 opened Apr 14, 2025 by ethanw-nv Loading…
1
[UVM] Add AXI sub sequences to soc_ifc environment
#831 opened Mar 18, 2025 by upadhyayulakiran Loading…
3
Auto-generation of regression yaml files for Calitpra_top regression runs.
#755 opened Feb 25, 2025 by anjpar Loading…
DCLS integration
#737 opened Feb 18, 2025 by kgugala Loading…
Add coverage report
#587 opened Sep 10, 2024 by kiryk Loading…
2
Add test for JTAG during uC reset
#554 opened Jul 4, 2024 by robertszczepanski Loading…
Patch 1.0 RTL with Lint Fixes enhancement New feature or request
#518 opened May 17, 2024 by calebofearth Loading…
@calebofearth
9
Fix PC setup after waking from clock gating in Verilator Future
#380 opened Jan 16, 2024 by robertszczepanski Loading…
12
ProTip! Exclude everything labeled bug with -label:bug.