Switch to use DCLS VeeR version

Signed-off-by: Karol Gugala <[email protected]>

Author: kgugala

src/integration/config/caliptra_top_tb.vf

@@ -218,6 +218,7 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_lib.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/mem_lib.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_regfile_if.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv
@@ -234,6 +235,7 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pmp.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_lockstep.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
 ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_bus_inf.sv
 ${CALIPTRA_ROOT}/src/ahb_lite_bus/rtl/ahb_lite_address_decoder.sv
@@ -621,4 +623,4 @@ ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_block_encrypt.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_state_db.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng_cmd_stage.sv
 ${CALIPTRA_ROOT}/src/csrng/rtl/csrng.sv
-${CALIPTRA_ROOT}/src/integration/rtl/caliptra_top.sv
+${CALIPTRA_ROOT}/src/integration/rtl/caliptra_top.sv

src/integration/rtl/caliptra_top.sv

@@ -439,6 +439,12 @@ always_comb begin
   el2_icache_stub.ic_tag_data_raw_pre = '0;
 end
 
+logic cptra_panic;
+
+`ifndef RV_LOCKSTEP_ENABLE
+assign cptra_panic = 1'b0;
+`endif
+
 el2_veer_wrapper rvtop (
 `ifdef CALIPTRA_FORCE_CPU_RESET
     .rst_l                  ( 1'b0 ),
@@ -577,6 +583,13 @@ el2_veer_wrapper rvtop (
     // Caliptra Memory Export Interface
     .el2_mem_export         (el2_mem_export),
 
+`ifdef RV_LOCKSTEP_ENABLE
+    // Shadow Core control
+    .disable_corruption_detection_i(1'b0),
+    .lockstep_err_injection_en_i(1'b0),
+    .corruption_detected_o(cptra_panic),
+`endif
+
     .core_id                ('0),
     .scan_mode              ( scan_mode ), // To enable scan mode
     .mbist_mode             ( 1'b0 )        // to enable mbist
@@ -1359,6 +1372,8 @@ soc_ifc_top1
     .fw_update_rst_window(fw_update_rst_window),
     //multiple cryptos operating at once, assert fatal error
     .crypto_error(crypto_error),
+    // DCLS error
+    .dcls_error  (cptra_panic ),
     //caliptra uncore jtag ports
     .cptra_uncore_dmi_reg_en( cptra_uncore_dmi_reg_en ),
     .cptra_uncore_dmi_reg_wr_en( cptra_uncore_dmi_reg_wr_en ),

src/integration/rtl/config_defines.svh

@@ -100,6 +100,7 @@
   `define CALIPTRA_RV_TOP     `CALIPTRA_TOP.caliptra_top_dut
 
   `define RV_TOP              `CALIPTRA_RV_TOP.rvtop
+  `define RV_LOCKSTEP_ENABLE 1
 
   `define CALIPTRA_ICG           cptra_clk_gate
 

src/riscv_core/veer_el2/config/compile.yml

@@ -54,6 +54,7 @@ targets:
       - $COMPILE_ROOT/rtl/lib/el2_lib.sv
       - $COMPILE_ROOT/rtl/lib/mem_lib.sv
       - $COMPILE_ROOT/rtl/lib/el2_mem_if.sv
+      - $COMPILE_ROOT/rtl/lib/el2_regfile_if.sv
       - $COMPILE_ROOT/rtl/lsu/el2_lsu_addrcheck.sv
       - $COMPILE_ROOT/rtl/lsu/el2_lsu_bus_buffer.sv
       - $COMPILE_ROOT/rtl/lsu/el2_lsu_bus_intf.sv
@@ -70,6 +71,7 @@ targets:
       - $COMPILE_ROOT/rtl/el2_pic_ctrl.sv
       - $COMPILE_ROOT/rtl/el2_pmp.sv
       - $COMPILE_ROOT/rtl/el2_veer.sv
+      - $COMPILE_ROOT/rtl/el2_veer_lockstep.sv
       - $COMPILE_ROOT/rtl/el2_veer_wrapper.sv
     tops: [el2_veer_wrapper]
   rtl_lint:

src/riscv_core/veer_el2/config/el2_veer_wrapper.vf

@@ -33,6 +33,7 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/axi4_to_ahb.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_lib.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/mem_lib.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_mem_if.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lib/el2_el2_regfile_if.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_addrcheck.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_buffer.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/lsu/el2_lsu_bus_intf.sv
@@ -49,4 +50,5 @@ ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_dma_ctrl.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pic_ctrl.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_pmp.sv
 ${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer.sv
-${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_lockstep.sv
+${CALIPTRA_ROOT}/src/riscv_core/veer_el2/rtl/el2_veer_wrapper.sv

src/riscv_core/veer_el2/rtl/common_defines.sv

@@ -244,6 +244,9 @@
 `define RV_INST_ACCESS_MASK5 'hffffffff
 `define RV_INST_ACCESS_MASK6 'hffffffff
 `define RV_INST_ACCESS_MASK7 'hffffffff
+`define RV_LOCKSTEP_DELAY 3
+`define RV_LOCKSTEP_ENABLE 1
+`define RV_LOCKSTEP_REGFILE_ENABLE 1
 `define RV_PMP_ENTRIES 64
 `define REGWIDTH 32
 `define RV_RESET_VEC 'h00000000

src/riscv_core/veer_el2/rtl/el2_param.vh

@@ -167,6 +167,9 @@ parameter el2_param_t pt = '{
 	INST_ACCESS_MASK6      : 36'h0FFFFFFFF  ,
 	INST_ACCESS_MASK7      : 36'h0FFFFFFFF  ,
 	LOAD_TO_USE_PLUS1      : 5'h00         ,
+	LOCKSTEP_DELAY         : 7'h03         ,
+	LOCKSTEP_ENABLE        : 5'h01         ,
+	LOCKSTEP_REGFILE_ENABLE : 5'h01        ,
 	LSU2DMA                : 5'h00         ,
 	LSU_BUS_ID             : 5'h01         ,
 	LSU_BUS_PRTY           : 6'h02         ,

src/riscv_core/veer_el2/rtl/el2_pdef.vh

@@ -168,6 +168,9 @@ typedef struct packed {
 	logic [35:0]     INST_ACCESS_MASK6;
 	logic [35:0]     INST_ACCESS_MASK7;
 	logic [4:0]      LOAD_TO_USE_PLUS1;
+	logic [6:0]      LOCKSTEP_DELAY;
+	logic [4:0]      LOCKSTEP_ENABLE;
+	logic [4:0]      LOCKSTEP_REGFILE_ENABLE;
 	logic [4:0]      LSU2DMA;
 	logic [4:0]      LSU_BUS_ID;
 	logic [5:0]      LSU_BUS_PRTY;

src/soc_ifc/rtl/soc_ifc_external_reg.rdl

@@ -28,7 +28,8 @@ reg {
     rw_rw_sticky_hw dccm_ecc_unc=0;     /* Uncorrectable double-bit error in DCCM */
     rw_rw_sticky_hw nmi_pin=0;          /* Non-Maskable Interrupt due to WDT timeout */
     rw_rw_sticky_hw crypto_err=0;       /* Crypto parallel operation error No Mask */ 
-    field {sw=r; hw=w;} rsvd[28]=28'h0;
+    rw_rw_sticky_hw dcls_error=0;       /* Non-Maskable DCLS error */
+    field {sw=r; hw=w;} rsvd[27]=27'h0;
 } CPTRA_HW_ERROR_FATAL;
 reg {
     name = "Hardware Error Non-Fatal";

src/soc_ifc/rtl/soc_ifc_reg.sv

@@ -415,6 +415,10 @@ module soc_ifc_reg (
                 logic next;
                 logic load_next;
             } crypto_err;
+            struct packed{
+                logic next;
+                logic load_next;
+            } dcls_error;
         } CPTRA_HW_ERROR_FATAL;
         struct packed{
             struct packed{
@@ -1505,6 +1509,9 @@ module soc_ifc_reg (
             struct packed{
                 logic value;
             } crypto_err;
+            struct packed{
+                logic value;
+            } dcls_error;
         } CPTRA_HW_ERROR_FATAL;
         struct packed{
             struct packed{
@@ -2428,6 +2435,30 @@ module soc_ifc_reg (
         end
     end
     assign hwif_out.CPTRA_HW_ERROR_FATAL.crypto_err.value = field_storage.CPTRA_HW_ERROR_FATAL.crypto_err.value;
+    // Field: soc_ifc_reg.CPTRA_HW_ERROR_FATAL.dcls_error
+    always_comb begin
+        automatic logic [0:0] next_c;
+        automatic logic load_next_c;
+        next_c = field_storage.CPTRA_HW_ERROR_FATAL.dcls_error.value;
+        load_next_c = '0;
+        if(decoded_reg_strb.CPTRA_HW_ERROR_FATAL && decoded_req_is_wr) begin // SW write 1 clear
+            next_c = field_storage.CPTRA_HW_ERROR_FATAL.dcls_error.value & ~(decoded_wr_data[4:4] & decoded_wr_biten[4:4]);
+            load_next_c = '1;
+        end else if(hwif_in.CPTRA_HW_ERROR_FATAL.dcls_error.we) begin // HW Write - we
+            next_c = hwif_in.CPTRA_HW_ERROR_FATAL.dcls_error.next;
+            load_next_c = '1;
+        end
+        field_combo.CPTRA_HW_ERROR_FATAL.dcls_error.next = next_c;
+        field_combo.CPTRA_HW_ERROR_FATAL.dcls_error.load_next = load_next_c;
+    end
+    always_ff @(posedge clk or negedge hwif_in.cptra_pwrgood) begin
+        if(~hwif_in.cptra_pwrgood) begin
+            field_storage.CPTRA_HW_ERROR_FATAL.dcls_error.value <= 1'h0;
+        end else if(field_combo.CPTRA_HW_ERROR_FATAL.dcls_error.load_next) begin
+            field_storage.CPTRA_HW_ERROR_FATAL.dcls_error.value <= field_combo.CPTRA_HW_ERROR_FATAL.dcls_error.next;
+        end
+    end
+    assign hwif_out.CPTRA_HW_ERROR_FATAL.dcls_error.value = field_storage.CPTRA_HW_ERROR_FATAL.dcls_error.value;
     // Field: soc_ifc_reg.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock
     always_comb begin
         automatic logic [0:0] next_c;
@@ -7046,7 +7077,8 @@ module soc_ifc_reg (
     assign readback_array[0][1:1] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.dccm_ecc_unc.value : '0;
     assign readback_array[0][2:2] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.nmi_pin.value : '0;
     assign readback_array[0][3:3] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.crypto_err.value : '0;
-    assign readback_array[0][31:4] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_ERROR_FATAL.rsvd.next : '0;
+    assign readback_array[0][4:4] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_FATAL.dcls_error.value : '0;
+    assign readback_array[0][31:5] = (decoded_reg_strb.CPTRA_HW_ERROR_FATAL && !decoded_req_is_wr) ? hwif_in.CPTRA_HW_ERROR_FATAL.rsvd.next : '0;
     assign readback_array[1][0:0] = (decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_no_lock.value : '0;
     assign readback_array[1][1:1] = (decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_prot_ooo.value : '0;
     assign readback_array[1][2:2] = (decoded_reg_strb.CPTRA_HW_ERROR_NON_FATAL && !decoded_req_is_wr) ? field_storage.CPTRA_HW_ERROR_NON_FATAL.mbox_ecc_unc.value : '0;