[TB] Fix a corner case in random DMA testbench that pushes data to FIFO during reset (#859)

* Don't push/pop from TB fifo during a rest

* Reduce default num_iterations to 50 to give reasonable run-time in nightly regressions

* Fix status message

* MICROSOFT AUTOMATED PIPELINE: Stamp 'cwhitehead-msft-dma-fifo-tb-fix' with updated timestamp and hash after successful run

Author: calebofearth

.github/workflow_metadata/pr_hash

@@ -1 +1 @@
-72bbc24d2efd78d87f5fc0e13b3230457a3f2611b3f5a6cb748d42beca67e9a6e9a6f5e5f4e67b87cb2b636344db0a14
+b4346b9efd43323f75f75e67316488e755110a4883acada97422d82c0396374133c12908180decb4d2d229b64bb4ee1f

.github/workflow_metadata/pr_timestamp

@@ -1 +1 @@
-1744826985
+1745565133

src/integration/tb/caliptra_top_tb_axi_fifo.sv

@@ -190,8 +190,8 @@ module caliptra_top_tb_axi_fifo #(
             rand_w_data <= $urandom;
             `endif
         end
-        rand_w_valid <= !fifo_clear && ((auto_push && (stall_down_count == 0)) || (rand_w_valid && !fifo_w_ready)); // Hold valid until data is accepted
-        rand_r_ready <=                 (auto_pop  && (stall_down_count == 0)) && fifo_r_valid;
+        rand_w_valid <= !fifo_clear && rst_n && ((auto_push && (stall_down_count == 0)) || (rand_w_valid && !fifo_w_ready)); // Hold valid until data is accepted
+        rand_r_ready <=                rst_n &&  (auto_pop  && (stall_down_count == 0)) && fifo_r_valid;
     end
 
     //=========================================================================-

src/integration/tb/caliptra_top_tb_services.sv

@@ -2348,8 +2348,8 @@ task initialize_caliptra_axi_sram;
                 end
 
                 // Progress reporting every 12.5% (8192 addresses)
-                if ((addr % AXI_SRAM_DEPTH/8) == 0) begin
-                    $display("  SRAM initialization progress: %0d%%", (addr * 100) / AXI_SRAM_DEPTH);
+                if (addr % (AXI_SRAM_DEPTH/8) == 0) begin
+                    $display("  SRAM initialization progress: %0d%% (addr: 0x%x)", (addr * 100) / AXI_SRAM_DEPTH, addr);
                 end
             end
 

src/integration/tb/dma_testcase_generator.sv

@@ -66,7 +66,7 @@ module dma_testcase_generator (
       logic [31:0] data;  // Assuming a 39-bit data format
 
       if (!$value$plusargs("NUM_ITERATIONS=%d", num_iterations)) begin 
-        num_iterations = 100; // Default
+        num_iterations = 50; // Default
       end
       if (num_iterations > 100) begin
           $fatal("num_iterations cannot exceed 100 due to width of dma_gen_block_size output signal...");