Release 2.0 signoff checklist

[calebofearth]

Overview

This issue tracks the outstanding items to complete prior to finalizing the 2.0 release version and provides public visibility to the sign-off protocol used for releases.
Discussions among contributors have been ongoing to agree on the proposed changes in any outstanding Pull Requests, in order to converge all required tests and sign-off protocols.

Checklist

• Regressions sign-off from Microsoft (after finalizing all PRs) @calebofearth
• Coverage sign-off @calebofearth
• Review RTL/Testbenches for TODO/FIXME items and fix or waive each occurrence @calebofearth
• FPGA validation @jlmahowa-amd
• Update HW Rev ID, HW_CONFIG registers @calebofearth Update HW_REV_ID and regenerate updated file-lists #770
• Update submodules to latest
• Complete Lint review @ravithakurAMD
• Complete CDC review @ravithakurAMD
• Complete RDC review @amullick007
• Formal Verification review @mojtaba-bisheh
• Update documentation
  • Add CDC constraints to integration specification
  • Add RDC constraints/waivers to integration specification @amullick007
  • Update release notes @calebofearth
  • README updates @calebofearth
    • Add CDC tool version @ravithakurAMD
    • Add RDC tool version @amullick007
  • Adams-Bridge README updates @mojtaba-bisheh
  • Add latest synthesis results to the integration specification RDC and Synthesis documentation update #858
  • Update version in integration spec, hardware spec, and release process
• Review GitHub issues for completion
• Tag the main branch with 2.0 @calebofearth
• Create 2.0 branch for FW regression consumption https://github.com/chipsalliance/caliptra-rtl/tree/patch_v2.0
• Update GitHub doc-gen workflow to publish register pages for all extant releases [ENV] Update doc-gen workflow to publish v2.0 register documentation #865

Pending Pull Requests to complete

[steven-bellock]

@calebofearth does this also include resolution of the TODOs and FIXMEs in the production RTL?

[calebofearth]

@calebofearth does this also include resolution of the TODOs and FIXMEs in the production RTL?

It wasn't; I just added this as a checklist item here: #656 and updated the issue just now.

[amullick007]

@calebofearth Created PR #858 for documentation update for RDC

[ravithakurAMD]

@calebofearth Created PR #862 for documentation update for CDC

[jlmahowa-amd]

Marking FPGA validation for 2.0 done.

Tested against FPGA built with:
Caliptra RTL:
commit 17a0f47 (origin/main, origin/HEAD)
Author: Caleb 11879229+calebofearth@users.noreply.github.com
Date: Wed Apr 16 17:44:25 2025 -0700
[TB] Fix block-size emulation for DMA test across warm resets (#856)
ADB RTL:
commit e754ce5ecc8fe0fbf2ef6fe333ae804f25073303 (HEAD -> main, origin/main, origin/HEAD)
Author: Michael Norris 108370498+Nitsirks@users.noreply.github.com
Date: Sun Apr 27 07:57:47 2025 -0700
[DOC] Updates to clarify memory requirements and streaming message mode (#140)
As of the writing of this caliptra-rtl has 2 new commits, but should be functionally the same.

caliptra-test: test result: ok. 117 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 1617.21s
      kat_halt_check_no_output and jtag_locked pass when enabled
      gdb_test fails. Error seems to be when connecting to GDB.

caliptra-drivers: test result: ok. 30 passed; 0 failed; 2 ignored; 0 measured; 0 filtered out; finished in 25.32s
      Ignored tests are mostly config dependent or require the lock-step timing of verilator/sw-emulator. Some ought to be able to be ran on FPGA:
            test_csrng_repetition_count passes
            test_csrng_adaptive_proportion passes
            test_trng_in_itrng_mode passes
            test_trng_in_etrng_mode crashed the FPGA - The FPGA was built for ITRNG so I did expect a failure. This seemed excessive though.

caliptra-rom: test result: FAILED. 138 passed; 13 failed; 4 ignored; 0 measured; 0 filtered out; finished in 401.60
12 tests are related to debug unlock, which is only available in SS mode. This FPGA built without so I believe these failures are expected
test_debug_unlock::test_dbg_unlock_manuf_invalid_token
test_debug_unlock::test_dbg_unlock_manuf_req_in_passive_mode
test_debug_unlock::test_dbg_unlock_manuf_success
test_debug_unlock::test_dbg_unlock_manuf_wrong_cmd
test_debug_unlock::test_dbg_unlock_prod_invalid_length
test_debug_unlock::test_dbg_unlock_prod_invalid_signature
test_debug_unlock::test_dbg_unlock_prod_invalid_token_challenge
test_debug_unlock::test_dbg_unlock_prod_success
test_debug_unlock::test_dbg_unlock_prod_unlock_levels_failure
test_debug_unlock::test_dbg_unlock_prod_unlock_levels_success
test_debug_unlock::test_dbg_unlock_prod_wrong_cmd
test_debug_unlock::test_dbg_unlock_prod_wrong_public_keys
This test initially failed but passed on rerun.
test_warm_reset::test_warm_reset_during_cold_boot_before_image_validation

caliptra-fmc: test result: ok. 5 passed; 0 failed; 0 ignored; 0 measured; 0 filtered out; finished in 64.53s
caliptra-hw-model: test result: ok. 6 passed; 0 failed; 6 ignored; 0 measured; 0 filtered out; finished in 10.23s

[calebofearth]

All items completed, v2.0 release is tagged. https://github.com/chipsalliance/caliptra-rtl/releases/tag/v2.0