Check i3c-core BUS_ENABLE for i3c readyness#3632
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swenson merged 1 commit intoApr 17, 2026
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…tests on FPGA, update FPGA bitstream (#3707) * [hw-model] Wait for subsystem boot completion in tests (#3561) * [hw-model] Wait for subsystem boot completion in tests * [gha] bump MCU ROM commit (cherry picked from commit 6139bb6) * Modify FPGA Subsystem model for PK Hash selection (#3551) mark PK hash as valid, and update OTP PQC key type encoding Signed-off-by: Amit Kumar-Hermosillo <amitkh@google.com> (cherry picked from commit b81d94b) * [gha] pin caliptra-mcu-sw to PR #1108 cherry-pick Switch CALIPTRA_MCU_COMMIT from the main-2.1 tip (7a47ca050e611bc93bfc5ff1fc7561466562a697) to the minimal commit that fixes the OTP PQC encoding without pulling in 25 unrelated changes: 8d5d93ef7e8c01536656eddd3206c4e626ca21bb (#1108 'Add default PK Hash selection logic to ROM', cherry-pick of e3fff33 from caliptra-mcu-sw main, paired with caliptra-sw #3551 b81d94b in 2.0). * [gha] include MCU PR #1145 fix in pinned commit Move CALIPTRA_MCU_COMMIT forward from 8d5d93ef (#1108 alone) to 6f3bea29ec2fd0d8613d78228cfd8e67726ef4ad on main-2.1. This adds 7 commits, most importantly #1145 'Don't stash MCU ROM by default' (cherry-pick of 52addd2), whose commit message explicitly notes it fixes 'many breakages in Core Runtime tests' — observed as test_activate_invalid_fw_id and other watchdog timeouts in the subsystem FPGA tests. * Check i3c-core BUS_ENABLE for i3c readyness (#3632) (cherry picked from commit 06b6aa0) * [ci] skip test_hek_seed_states, OCP LOCK tests on FPGA subsystem profile caliptra-mcu-sw#1135 (a04a9c28) on main-2.1 gated all set_ocp_lock_fuses code behind the 'ocp-lock' Cargo feature, but the FPGA mcu-rom-fpga crate does not currently expose an 'ocp-lock' feature pass-through. * [fpga] update subsystem bitstream to runtime_2d3a0232.pdi caliptra-mcu-sw main-2.1 commit 7ec1320a (#1202) updated the subsystem FPGA bitstream and noted 'Release TTI reset / Use updated caliptra-sw with different i3c polling check'. Our caliptra-sw branch was still using the older runtime_6a9856ff.pdi from MCU 2026-03-17, which hangs Caliptra ROM's recovery-FIFO payload_available signal during the flash-boot path on MCU >= 7ec1320a. Specifically: when CI ran test_activate_invalid_fw_id with MCU 6f3bea29 and the old bitstream, Caliptra ROM hung indefinitely in 'while !self.dma.payload_available() {}' (drivers/src/dma.rs:811) after MCU wrote indirect_fifo_ctrl_1 with the image size. The MCU WDT then fired at 800M cycles and triggered a cold reset, which itself hung because the device was still in flash-boot input-wires state. Pin to the same bitstream caliptra-mcu-sw main-2.1 uses (runtime_2d3a0232.pdi). * [ci] temporarily skip test_encrypted_firmware_decrypt_dma on FPGA subsystem The test consistently hits the 180s nextest slow-timeout in CI under MCU 6f3bea29. The MCU runs through the encrypted boot flow successfully (CM_IMPORT, CM_AES_GCM_DECRYPT_DMA, MCU ROM digest verification), then triggers a warm reset to enter FwBoot, after which the test framework appears to be waiting on something that never settles. Disabling temporarily so the rest of the FPGA subsystem suite can land; investigating the root cause separately. The new MCU ROM's stash flow defaults to off (PR #1145), but the cold-boot path still computes/checks the ROM digest and unconditionally triggers a warm reset at the end via mci.trigger_warm_reset(), so this may be a state-machine timing issue in either the test framework's wait-for-COLD_BOOT_FLOW_COMPLETE logic or the MCU FwBoot path under encrypted boot. --------- Signed-off-by: Amit Kumar-Hermosillo <amitkh@google.com> Co-authored-by: Amit Kumar <51718056+amit-kumarh@users.noreply.github.com> Co-authored-by: Amit Kumar <amitkh@google.com> Co-authored-by: jlmahowa-amd <102375203+jlmahowa-amd@users.noreply.github.com>
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