[OCP-LOCK] Enable encryption engine interacting tests on subsystem FPGA#3640
[OCP-LOCK] Enable encryption engine interacting tests on subsystem FPGA#3640GwangbaeCHOI wants to merge 1 commit into
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GwangbaeCHOI
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Apr 21, 2026
GwangbaeCHOI
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- Enable DERIVE_MEK tests ([OCP-LOCK]: Enable Derive MEK tests on subsystem FPGA #3362)
- Enable CLEAR_KEY_CACHE tests
- Enable LOAD_MEK tests
- Enable UNLOAD_MEK tests
| error_code, _: 19, 16; | ||
| ready_bit, _: 31; | ||
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| #[cfg(any(feature = "fpga_realtime", feature = "fpga_subsystem"))] |
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These codes are not really needed for fpga_realtime. But I found that the current fpga-subsystem tests on MCU uses fpga-realtime ROM of Caliptra, and that's why I added fpga_realtime feature here.
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Confusingly, fpga_realtime in MCU == fpga_subsystem in Caliptra.
- Enable DERIVE_MEK tests (chipsalliance#3362) - Enable CLEAR_KEY_CACHE tests - Enable LOAD_MEK tests - Enable UNLOAD_MEK tests
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| fn realtime_encryption_engine_register_handler( |
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This thread simulates the encryption engine similar to the thread for internal TRNG. Since we don't have exactly same RW access to registers, especially the RDY bit of CTRL register, There are additional codes to retain the RDY bit.
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Should we make a change to the FPGA wrapper RTL?
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If we can make RDY bit sticky, it would be better
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| // To maintain the RDY bit to be set | ||
| #[cfg(any(feature = "fpga_realtime", feature = "fpga_subsystem"))] | ||
| ctrl.set_ready_bit(true); |
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RDY bit will remain 1 after clearing the register.
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Why does this bit need special treatment on the FPGA? What would it take to eliminate this feature flagged code and simplify the firmware?
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WIthin the FPGA wrapper, CTRL register is RW. So, Caliptra can overwrite RDY bit which supposed to be read-only. If we can make RDY bit to be sticky, we won't need this code.
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Thanks @GwangbaeCHOI let me see if we can make a change to the FPGA Wrapper
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@GwangbaeCHOI sounds like we can make that happen, want to wait for a new bitstream or move ahead ?
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I can wait. So that we won't need to update again.
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| // To maintain the RDY bit to be set | ||
| #[cfg(any(feature = "fpga_realtime", feature = "fpga_subsystem"))] | ||
| ctrl.set_ready_bit(true); |
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To keep RDY bit to 1 after executing a command
| pub realtime_encryption_engine_exit_flag: Arc<AtomicBool>, | ||
| pub realtime_encryption_engine_paused: Arc<AtomicBool>, |
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nit: I think you can skip using Arc to wrap the AtomicBool? IIRC it should be safe to copy and share the AtomicBools across threads
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