test: read IDevID CSR during boot to fix subsystem CSR-stress hang#3877
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swenson wants to merge 3 commits into
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test: read IDevID CSR during boot to fix subsystem CSR-stress hang#3877swenson wants to merge 3 commits into
swenson wants to merge 3 commits into
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test_generate_csr_envelop_stress uses unbounded step_until calls, so when a boot fails to reach the expected state the test hangs until nextest's slow timeout (~90 min in nightly), which stalls and fails the whole nightly run. Add HwModel::step_until_or_timeout (bounded like the existing step_until_boot_status, 30M cycles) and use it for the idevid_csr_ready, ready_for_mb_processing, and ready_for_runtime waits in the CSR envelope path. A hung boot now panics in seconds with the awaited condition named, instead of waiting for the harness timeout.
The CSR stress test deferred reading the IDevID CSR until after model construction, so on the FPGA subsystem the host's mailbox read raced the MCU's RI_DOWNLOAD_FIRMWARE and the test hung until the harness timeout. Drain the CSR at one point on every backend: when idevid_csr_ready asserts during boot, via the model's rom_callback (gated by a new BootParams::read_idevid_csr_in_callback). On the subsystem this runs while the MCU is still held at the download gate, so there's no race. Firmware is supplied via BootParams so the model still boots to runtime for the LDEV/FMC/RT cert checks. Boot waits are also bounded so a stall fails fast with a register dump instead of timing out.
swenson
requested review from
JohnTraverAmd,
ajisaxena,
clundin25,
fdamato,
jhand2,
jlmahowa-amd,
korran,
mhatrevi,
ternst-nv,
timothytrippel,
vsonims and
zhalvorsen
as code owners
June 12, 2026 17:29
The CSR-during-boot fix relies on rom_callback firing when idevid_csr_ready asserts, but the fpga_realtime and verilated models neither stored nor ran the callback, so test_generate_csr_envelop failed with "CSR was not captured" on FPGA realtime. Store the callback and run it from run_idevid_csr_callback, matching the emulated and subsystem models.
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The CSR stress test deferred reading the IDevID CSR until after model
construction, so on the FPGA subsystem the host's mailbox read raced the
MCU's RI_DOWNLOAD_FIRMWARE and the test hung until the harness timeout.
Drain the CSR at one point on every backend: when idevid_csr_ready asserts
during boot, via the model's rom_callback (gated by a new
BootParams::read_idevid_csr_in_callback). On the subsystem this runs while
the MCU is still held at the download gate, so there's no race. Firmware is
supplied via BootParams so the model still boots to runtime for the
LDEV/FMC/RT cert checks. Boot waits are also bounded so a stall fails fast
with a register dump instead of timing out.