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Merge branch 'master' into release
2 parents 435c03b + e2c5c12 commit 10e42a4

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4 files changed

+51
-15
lines changed

4 files changed

+51
-15
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build.sbt

+10-6
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ def javacOptionsVersion(scalaVersion: String): Seq[String] = {
3232

3333
lazy val commonSettings = Seq (
3434
organization := "edu.berkeley.cs",
35-
version := "3.0-SNAPSHOT_2017-09-14",
35+
version := "3.0-SNAPSHOT_2017-09-27",
3636
git.remoteRepo := "[email protected]:freechipsproject/chisel3.git",
3737
autoAPIMappings := true,
3838
scalaVersion := "2.11.11",
@@ -92,7 +92,7 @@ lazy val publishSettings = Seq (
9292
}
9393
)
9494

95-
val defaultVersions = Map("firrtl" -> "1.0-SNAPSHOT_2017-09-14")
95+
val defaultVersions = Map("firrtl" -> "1.0-SNAPSHOT_2017-09-27")
9696

9797
lazy val chiselSettings = Seq (
9898
name := "chisel3",
@@ -140,9 +140,7 @@ lazy val chisel = (project in file(".")).
140140
// Prevent separate JARs from being generated for coreMacros and chiselFrontend.
141141
dependsOn(coreMacros % "compile-internal;test-internal").
142142
dependsOn(chiselFrontend % "compile-internal;test-internal").
143-
// The following is required until sbt-scoverage correctly deals with inDependencies
144-
// Unfortunately, it also revives publishing of the subproject jars. Disable until the latter is resolved (again).
145-
//aggregate(coreMacros, chiselFrontend).
143+
aggregate(coreMacros, chiselFrontend).
146144
settings(
147145
scalacOptions in Test ++= Seq("-language:reflectiveCalls"),
148146
scalacOptions in Compile in doc ++= Seq(
@@ -152,7 +150,13 @@ lazy val chisel = (project in file(".")).
152150
"-doc-title", name.value,
153151
"-doc-root-content", baseDirectory.value+"/root-doc.txt"
154152
),
155-
aggregate in doc := false,
153+
// Disable aggregation in general, but enable it for specific tasks.
154+
// Otherwise we get separate Jar files for each subproject and we
155+
// go to great pains to package all chisel3 core code in a single Jar.
156+
// If you get errors indicating coverageReport is undefined, be sure
157+
// you have sbt-scoverage in project/plugins.sbt
158+
aggregate := false,
159+
aggregate in coverageReport := true,
156160
// Include macro classes, resources, and sources main JAR.
157161
mappings in (Compile, packageBin) ++= (mappings in (coreMacros, Compile, packageBin)).value,
158162
mappings in (Compile, packageSrc) ++= (mappings in (coreMacros, Compile, packageSrc)).value,

chiselFrontend/src/main/scala/chisel3/core/Binding.scala

+5-2
Original file line numberDiff line numberDiff line change
@@ -88,11 +88,14 @@ sealed trait ConstrainedBinding extends TopBinding {
8888
def location = Some(enclosure)
8989
}
9090

91+
// A binding representing a data that cannot be (re)assigned to.
92+
sealed trait ReadOnlyBinding extends TopBinding
93+
9194
// TODO literal info here
92-
case class LitBinding() extends UnconstrainedBinding
95+
case class LitBinding() extends UnconstrainedBinding with ReadOnlyBinding
9396
// TODO(twigg): Ops between unenclosed nodes can also be unenclosed
9497
// However, Chisel currently binds all op results to a module
95-
case class OpBinding(enclosure: UserModule) extends ConstrainedBinding
98+
case class OpBinding(enclosure: UserModule) extends ConstrainedBinding with ReadOnlyBinding
9699
case class MemoryPortBinding(enclosure: UserModule) extends ConstrainedBinding
97100
case class PortBinding(enclosure: BaseModule) extends ConstrainedBinding
98101
case class RegBinding(enclosure: UserModule) extends ConstrainedBinding

chiselFrontend/src/main/scala/chisel3/core/Data.scala

+8
Original file line numberDiff line numberDiff line change
@@ -267,6 +267,10 @@ abstract class Data extends HasId {
267267
if (connectCompileOptions.checkSynthesizable) {
268268
requireIsHardware(this, "data to be connected")
269269
requireIsHardware(that, "data to be connected")
270+
this.topBinding match {
271+
case _: ReadOnlyBinding => throwException(s"Cannot reassign to read-only $this")
272+
case _ => // fine
273+
}
270274
try {
271275
MonoConnect.connect(sourceInfo, connectCompileOptions, this, that, Builder.forcedUserModule)
272276
} catch {
@@ -283,6 +287,10 @@ abstract class Data extends HasId {
283287
if (connectCompileOptions.checkSynthesizable) {
284288
requireIsHardware(this, s"data to be bulk-connected")
285289
requireIsHardware(that, s"data to be bulk-connected")
290+
(this.topBinding, that.topBinding) match {
291+
case (_: ReadOnlyBinding, _: ReadOnlyBinding) => throwException(s"Both $this and $that are read-only")
292+
case _ => // fine
293+
}
286294
try {
287295
BiConnect.connect(sourceInfo, connectCompileOptions, this, that, Builder.forcedUserModule)
288296
} catch {

src/test/scala/chiselTests/MultiAssign.scala

+28-7
Original file line numberDiff line numberDiff line change
@@ -26,21 +26,42 @@ class LastAssignTester() extends BasicTester {
2626
}
2727
}
2828

29-
class ReassignmentTester() extends BasicTester {
30-
val test = 15.U
31-
test := 7.U
32-
}
33-
3429
class MultiAssignSpec extends ChiselFlatSpec {
3530
"The last assignment" should "be used when multiple assignments happen" in {
3631
assertTesterPasses{ new LastAssignTester }
3732
}
3833
}
3934

4035
class IllegalAssignSpec extends ChiselFlatSpec {
41-
"Reassignments to non-wire types" should "be disallowed" in {
36+
"Reassignments to literals" should "be disallowed" in {
37+
intercept[chisel3.internal.ChiselException] {
38+
elaborate{ new BasicTester {
39+
15.U := 7.U
40+
}}
41+
}
42+
}
43+
44+
"Reassignments to ops" should "be disallowed" in {
45+
intercept[chisel3.internal.ChiselException] {
46+
elaborate{ new BasicTester {
47+
(15.U + 1.U) := 7.U
48+
}}
49+
}
50+
}
51+
52+
"Reassignments to bit slices" should "be disallowed" in {
53+
intercept[chisel3.internal.ChiselException] {
54+
elaborate{ new BasicTester {
55+
(15.U)(1, 0) := 7.U
56+
}}
57+
}
58+
}
59+
60+
"Bulk-connecting two read-only nodes" should "be disallowed" in {
4261
intercept[chisel3.internal.ChiselException] {
43-
assertTesterFails{ new ReassignmentTester }
62+
elaborate{ new BasicTester {
63+
(15.U + 1.U) <> 7.U
64+
}}
4465
}
4566
}
4667
}

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