Search results

value emitVerilog is not a member of circt.stage.ChiselStage

Status: Open.

#4603 In chipsalliance/chisel;

· quantrpeter opened on Jan 9, 2025

SingleTargetAnnotations will report java.lang.NumberFormatException when indexing a Vec chisel type

Status: Open.

#4575 In chipsalliance/chisel;

· davine47 opened on Dec 24, 2024

Regarding the loss of active reset behavior of Reg or being overridden by RegInit.

Status: Open.

#4567 In chipsalliance/chisel;

· linmoIO opened on Dec 18, 2024

chisel3.util.Queue not working with SInt

bug

Status: Open.

#4536 In chipsalliance/chisel;

· jiegec opened on Nov 27, 2024

Semantic Inconsistency in Intermediate FIRRTL File During Compilation: Incorrect reg Emission Instead of node and Loss of Memory readUnderWrite Behavior

Status: Open.

#4526 In chipsalliance/chisel;

· linmoIO opened on Nov 25, 2024

Initialize (FPGA) memory in Chisel 6

Status: Open.

#4496 In chipsalliance/chisel;

· schoeberl opened on Nov 6, 2024

Need for explicit widths in BlackBox parameters

Status: Open.

#4488 In chipsalliance/chisel;

· HakamAtassi opened on Oct 26, 2024

Selecting instances when using D/I and Class Property types crashes

Status: Open.

#4476 In chipsalliance/chisel;

· jackkoenig opened on Oct 16, 2024

Layers not emitted when used as colors of probes with separate elaboration

Status: Open.

#4469 In chipsalliance/chisel;

· dtzSiFive opened on Oct 15, 2024

PriorityMux drops arguments if input sequences are not the same size

bug

good first issueAn issue whose fix is simple. Perfect for a new developer wanting to get involved!An issue whose fix is simple. Perfect for a new developer wanting to get involved!

Status: Open.

#4444 In chipsalliance/chisel;

· jackkoenig opened on Oct 4, 2024

SyncReadMem ruw (ReadUnderWrite) parameter has no effect

Status: Open.

#4433 In chipsalliance/chisel;

· maxbjurling opened on Oct 2, 2024

Probe color should be checked for read

bug

Status: Open.

#4406 In chipsalliance/chisel;

· dtzSiFive opened on Sep 19, 2024