Merge branch 'master' into release; bump version

Author: ucbjrl

Makefile

@@ -57,7 +57,7 @@ ifneq (,$(RM_DIRS))
 endif
 
 scaladoc:
-	$(SBT) $(SBT_FLAGS) doc
+	$(SBT) $(SBT_FLAGS) unidoc
 
 site:
 	$(SBT) $(SBT_FLAGS) make-site

build.sbt

@@ -32,7 +32,7 @@ def javacOptionsVersion(scalaVersion: String): Seq[String] = {
 
 lazy val commonSettings = Seq (
   organization := "edu.berkeley.cs",
-  version := "3.0.0-RC1",
+  version := "3.0.0-RC2",
   git.remoteRepo := "[email protected]:freechipsproject/chisel3.git",
   autoAPIMappings := true,
   scalaVersion := "2.11.11",
@@ -92,7 +92,7 @@ lazy val publishSettings = Seq (
   }
 )
 
-val defaultVersions = Map("firrtl" -> "1.0.0-RC1")
+val defaultVersions = Map("firrtl" -> "1.0.0-RC2")
 
 lazy val chiselSettings = Seq (
   name := "chisel3",

chiselFrontend/src/main/scala/chisel3/internal/Builder.scala

@@ -166,7 +166,7 @@ private[chisel3] object Builder {
 
   // Initialize any singleton objects before user code inadvertently inherits them.
   private def initializeSingletons(): Unit = {
-    val dummy = DontCare
+    val dummy = core.DontCare
   }
   def idGen: IdGen = dynamicContext.idGen
   def globalNamespace: Namespace = dynamicContext.globalNamespace

src/test/scala/chiselTests/InvalidateAPISpec.scala

@@ -66,13 +66,13 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers {
     val nElements = 5
     class ModuleWithoutDontCare extends Module {
       val io = IO(new Bundle {
-        val ins = Input(Vec(nElements, Bool()))
+        val outs = Output(Vec(nElements, Bool()))
       })
-      io.ins <> DontCare
+      io.outs <> DontCare
     }
     val firrtlOutput = myGenerateFirrtl(new ModuleWithoutDontCare)
     for (i <- 0 until nElements)
-     firrtlOutput should include(s"io.ins[$i] is invalid")
+     firrtlOutput should include(s"io.outs[$i] is invalid")
   }
 
   property("a Vec with a DontCare should emit a Firrtl \"is invalid\" with Strict CompileOptions and mono connect") {
@@ -161,4 +161,48 @@ class InvalidateAPISpec extends ChiselPropSpec with Matchers {
 
     compileFirrtl(new ModuleWithConditionalAndOtherwiseAssignment)
   }
+
+  property("an output without a DontCare should NOT emit a Firrtl \"is invalid\" with overriden NotStrict CompileOptions") {
+    import chisel3.core.ExplicitCompileOptions.NotStrict
+    class ModuleWithoutDontCare extends Module {
+      override val compileOptions = chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true)
+      val io = IO(new TrivialInterface)
+      io.out := io.in
+    }
+    val firrtlOutput = myGenerateFirrtl(new ModuleWithoutDontCare)
+    firrtlOutput should not include("is invalid")
+  }
+
+  property("an output without a DontCare should NOT emit a Firrtl \"is invalid\" with overriden NotStrict CompileOptions module definition") {
+    import chisel3.core.ExplicitCompileOptions.NotStrict
+    abstract class ExplicitInvalidateModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = true))
+    class ModuleWithoutDontCare extends ExplicitInvalidateModule {
+      val io = IO(new TrivialInterface)
+      io.out := io.in
+    }
+    val firrtlOutput = myGenerateFirrtl(new ModuleWithoutDontCare)
+    firrtlOutput should not include("is invalid")
+  }
+
+  property("an output without a DontCare should emit a Firrtl \"is invalid\" with overriden Strict CompileOptions") {
+    import chisel3.core.ExplicitCompileOptions.Strict
+    class ModuleWithoutDontCare extends Module {
+      override val compileOptions = chisel3.core.ExplicitCompileOptions.Strict.copy(explicitInvalidate = false)
+      val io = IO(new TrivialInterface)
+      io.out := io.in
+    }
+    val firrtlOutput = myGenerateFirrtl(new ModuleWithoutDontCare)
+    firrtlOutput should include("is invalid")
+  }
+
+  property("an output without a DontCare should emit a Firrtl \"is invalid\" with overriden Strict CompileOptions module definition") {
+    import chisel3.core.ExplicitCompileOptions.Strict
+    abstract class ImplicitInvalidateModule extends Module()(chisel3.core.ExplicitCompileOptions.NotStrict.copy(explicitInvalidate = false))
+    class ModuleWithoutDontCare extends ImplicitInvalidateModule {
+      val io = IO(new TrivialInterface)
+      io.out := io.in
+    }
+    val firrtlOutput = myGenerateFirrtl(new ModuleWithoutDontCare)
+    firrtlOutput should include("is invalid")
+  }
 }