Fix emitted FIRRTL for dynamic index of size 0 Vec (#4275) (#4276)

This is currently a warning but not yet an error so we need to emit
legal FIRRTL.

(cherry picked from commit d5ccf48)

Co-authored-by: Jack Koenig <[email protected]>

Author: mergify[bot]

core/src/main/scala/chisel3/Aggregate.scala

@@ -154,7 +154,8 @@ trait VecFactory extends SourceInfoDoc {
     implicit sourceInfo: SourceInfo
   ): UInt = {
     val w = (n - 1).bitLength
-    if (n <= 1) 0.U
+    if (n <= 1) WireInit(0.U) // Need the Wire otherwise we emit vec[0] which is illegal FIRRTL.
+    // Other cases do not need a Wire because the literal is truncated to fit.
     else if (idx.width.known && idx.width.get <= w) idx
     else if (idx.width.known) idx(w - 1, 0)
     else (idx | 0.U(w.W))(w - 1, 0)

src/test/scala/chiselTests/Vec.scala

@@ -466,4 +466,18 @@ class VecSpec extends ChiselPropSpec with Utils {
     }))
     log should be("")
   }
+
+  property("Indexing a size 0 Vec should warn but also emit legal FIRRTL") {
+    val (log, chirrtl) = grabLog(emitCHIRRTL(new RawModule {
+      val vec = IO(Input(Vec(0, UInt(8.W))))
+      val idx = IO(Input(UInt(2.W)))
+      val out = IO(Output(UInt(8.W)))
+      out := vec(idx)
+    }))
+    log should include("Cannot extract from Vec of size 0.")
+    chirrtl should include("input vec : UInt<8>[0]")
+    chirrtl should include("wire _out_WIRE : UInt")
+    chirrtl should include("connect _out_WIRE, UInt<1>(0h0)")
+    chirrtl should include("connect out, vec[_out_WIRE]")
+  }
 }