Partial FASM File Generation Support

patch_mem.py

@@ -12,7 +12,12 @@
 
 
 def patch_mem(
-    fasm=None, init=None, mdd=None, outfile=None, selectedMemToPatch=None
+    fasm=None,
+    init=None,
+    mdd=None,
+    outfile=None,
+    selectedMemToPatch=None,
+    wantPartialFASM=False
 ):
     assert fasm is not None
     assert init is not None
@@ -54,10 +59,25 @@ def patch_mem(
         mdd=mdd_data
     )
 
-    # Merge the non-INIT tuples (cleared_tups) in with the new memory tuples
-    # to create a new complete FASM file
-    merged = merge_tuples(cleared_tups=cleared_tups, mem_tups=memfasm)
-    write_fasm(outfile, merged)
+    if wantPartialFASM == True:
+        # Find any and all non-INIT tuples located at the patched BRAM
+        for data in mdd_data:
+            tile = data.tile
+            frame_tups = []
+            for tup in cleared_tups:
+                if tup[0] != None:
+                    if tup[0].feature.find(tile) != -1:
+                        frame_tups.append(tup)
+        # Merge the newly found non_INIT tuples with the new memory tuples
+        # to create a partial FASM file
+        merged = merge_tuples(cleared_tups=frame_tups, mem_tups=memfasm)
+        write_fasm(outfile, merged)
+    else:
+        # Merge all non-INIT tuples (cleared_tups) in with the new memory tuples
+        # to create a new complete FASM file
+        merged = merge_tuples(cleared_tups=cleared_tups, mem_tups=memfasm)
+        write_fasm(outfile, merged)
+
     print("Patching done...")
 
 
@@ -90,6 +110,22 @@ def read_fasm(fname):
 
 
 if __name__ == "__main__":
-    assert len(sys.argv) == 6, \
-           "Usage: patch_mem fasmFile newMemContents mddFile patchedFasmFile memName"
-    patch_mem(sys.argv[1], sys.argv[2], sys.argv[3], sys.argv[4], sys.argv[5])
+    if len(sys.argv) == 6:
+        patch_mem(
+            sys.argv[1], sys.argv[2], sys.argv[3], sys.argv[4], sys.argv[5]
+        )
+    elif len(sys.argv) == 7:
+        if sys.argv[6] == "partial":
+            patch_mem(
+                sys.argv[1], sys.argv[2], sys.argv[3], sys.argv[4],
+                sys.argv[5], True
+            )
+        else:
+            print(
+                "wantPartialFASM must be specified as 'partial', or left blank to get a full file"
+            )
+    else:
+        print(
+            "Usage: patch_mem fasmFile newMemContents mddFile patchedFasmFile memName [wantPartialFASM]{partial}"
+        )
+    exit(1)

samples/128b1_dual/gen.tcl

@@ -25,5 +25,5 @@ mddMake ./mapping
 
 write_edif -force ./vivado/${::env(DESIGN_NAME)}.edif
 write_checkpoint -force ./vivado/${::env(DESIGN_NAME)}.dcp
-write_bitstream -force ./vivado/${::env(DESIGN_NAME)}.bit
+write_bitstream -logic_location_file -force ./vivado/${::env(DESIGN_NAME)}.bit
 

singletests/32kb1/mapping.mdd

@@ -0,0 +1,25 @@
+DESIGN design_1
+PART xc7a50tfgg484-1
+
+CELL mem/ram_reg
+  TILE BRAM_L_X6Y15
+  CELLTYPE RAMB36E1
+  LOC RAMB36_X0Y3
+  MEM.PORTA.DATA_BIT_LAYOUT p0_d1
+  RTL_RAM_NAME ram
+  RAM_EXTENSION_A NONE
+  RAM_MODE TDP
+  READ_WIDTH_A 1
+  READ_WIDTH_B 1
+  WRITE_WIDTH_A 1
+  WRITE_WIDTH_B 1
+  RAM_OFFSET NONE
+  BRAM_ADDR_BEGIN 0
+  BRAM_ADDR_END 32767
+  BRAM_SLICE_BEGIN 0
+  BRAM_SLICE_END 0
+  RAM_ADDR_BEGIN NONE
+  RAM_ADDR_END NONE
+  RAM_SLICE_BEGIN NONE
+  RAM_SLICE_END NONE
+ENDCELL

singletests/32kb1/prepTest.sh

@@ -0,0 +1 @@
+$MEM_PATCH_DIR/testing/generate_tests_script.sh /tmp 1 32k 32768 allones

singletests/32kb1/vivado/32kb1.sv

@@ -0,0 +1,46 @@
+module top(
+input logic clk,
+input logic[14:0] raddr,
+input logic[14:0] waddr,
+input logic [0:0] din,
+output logic [0:0] dout,
+input logic reset);
+
+memory #("tests/master/32kb1/init/init.mem", 1, 1, 32768) mem(
+	.clk(clk), 
+	.raddr(raddr), 
+	.waddr(waddr), 
+	.din(din), 
+	.dout(dout), 
+	.reset(reset));
+
+endmodule
+
+module memory #(
+    parameter F_INIT="init.txt",
+    parameter INIT_ISHEX = 1,
+    //parameter WID_MEM=16,
+    //parameter DEPTH_MEM=2048)
+    parameter WID_MEM=1,
+    parameter DEPTH_MEM=16384)    
+    (input logic clk,
+    input logic[14:0] raddr,
+    input logic[14:0] waddr,
+    input logic[WID_MEM-1:0] din,
+    output logic[WID_MEM-1:0] dout,
+    input logic reset);
+
+    (* ram_style = "block" *) logic [WID_MEM-1:0] ram [0:DEPTH_MEM-1];
+
+    if (INIT_ISHEX)
+        initial $readmemh(F_INIT, ram);
+        //initial $readmemh ("../init/1_by_16k.txt",ram);
+    else
+        initial $readmemb(F_INIT,ram);
+
+    always_ff @(posedge clk) begin
+        dout <= ram[raddr];
+        ram[waddr]<= din; 
+    end
+endmodule
+