Search results

BOOM does not initialize io.core.rocc.mem.store_pending

Status: Open.

#3819 In chipsalliance/rocket-chip;

· doodidude opened on Jul 15, 2026

[Security] Hypervisor NonBlockingDCache does not invalidate DTLB for HFENCE.VVMA/GVMA

Status: Open.

#3817 In chipsalliance/rocket-chip;

· wang02020119 opened on Jul 8, 2026

[Bug] First VS-mode sstatus read returns host FS/SD view instead of VS-visible state

Status: Open.

#3816 In chipsalliance/rocket-chip;

· jf-cc727 opened on Jul 4, 2026

[Bug] hedeleg writes are masked to zero in H-enabled Rocket

Status: Open.

#3815 In chipsalliance/rocket-chip;

· jf-cc727 opened on Jul 4, 2026

[Bug] PMP cfg reset/readback exposes reserved R/W encoding after reset

Status: Open.

#3814 In chipsalliance/rocket-chip;

· jf-cc727 opened on Jul 4, 2026

[Bug] CSR: MPRV-mediated PMP fault raises wrong exception code (mcause=2 or 3 instead of 5 or 7)

Status: Open.

#3812 In chipsalliance/rocket-chip;

· Security-HC opened on Jun 26, 2026

[Bug] CSR: S-mode access to M-mode CSRs raises wrong exception code (mcause=1 instead of mcause=2)

Status: Open.

#3811 In chipsalliance/rocket-chip;

· Security-HC opened on Jun 26, 2026

[BUG] Rocket DefaultSmallConfig traps S-mode fetch from an X-only PMP region

Status: Open.

#3810 In chipsalliance/rocket-chip;

· KnightGOKU opened on Jun 18, 2026

[BUG] Rocket DefaultSmallConfig does not trap MPRV=S store denied by PMP

Status: Open.

#3809 In chipsalliance/rocket-chip;

· KnightGOKU opened on Jun 16, 2026

Rocket hangs instead of taking load page fault when PMP also denies the translated address

Status: Open.

#3808 In chipsalliance/rocket-chip;

· jimmymtest opened on Jun 7, 2026

ASIdBits parameter always set to 0

Status: Open.

#3787 In chipsalliance/rocket-chip;

· ibyteibit opened on Apr 18, 2026

ALU shiftReverse includes FN_ROR unconditionally, leaving residual logic when useZbb=false

Status: Open.

#3784 In chipsalliance/rocket-chip;

· yiidtw opened on Mar 23, 2026