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formatterVerilog code formatter issuesVerilog code formatter issues
Description
Behavior around module instantiation wrapping doesn't seem desirable. Whenever only one port and/or parameter is given, the instantiation is done on one line (as long as it fits on the line). If 2 ports or 2 parameters are given, then the instantiation style is wrapped, even if it does fit on one line.
Test case
module_name #(
.Param1(Param1)
) only_one_param_or_port (
.port_i(a_i)
);
module_name #(
.Param1(Param1),
.Param2(Param2)
) two_or_more_param_or_ports (
.port_i(a_i)
);
module_name fits_on_one_line (
.port_i(a_i),
.port_o(b_o)
);Actual output
module_name #(.Param1(Param1)) only_one_param_or_port (.port_i(a_i));
module_name #(
.Param1(Param1),
.Param2(Param2)
) two_or_more_param_or_ports (
.port_i(a_i)
);
module_name fits_on_one_line (
.port_i(a_i),
.port_o(b_o)
);Include any possible diagnostic messages from the formatter.
The output I desire
I always want to wrap my instantiations, even if it fits on one line.
module_name #(
.Param1(Param1)
) only_one_param_or_port (
.port_i(a_i)
);
module_name #(
.Param1(Param1),
.Param2(Param2)
) two_or_more_param_or_ports (
.port_i(a_i)
);
module_name fits_on_one_line (
.port_i(a_i),
.port_o(b_o)
);Another Output Option that Some May Prefer
Some may prefer making the instantiation fit on one line if it is <= the character limit.
module_name fits_on_one_line (.port_i(a_i), .port_o(b_o));Metadata
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formatterVerilog code formatter issuesVerilog code formatter issues
Type
Projects
Status
v1.1 - features