Skip to content

Pull requests: chipsalliance/verible

New pull request New
40 Open 1,447 Closed
40 Open 1,447 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Assigned to nobody Loading
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

Prefer clang-format-19 in run-format.sh
#2582 opened Aug 18, 2026 by kbrunham-intel Contributor Loading…
3 of 4 tasks
1
1
Fix formatter abort on non-ANSI wire signed ports
#2581 opened Aug 18, 2026 by kbrunham-intel Contributor Loading…
2 of 3 tasks
3
1
Fix formatter dropping function ports when packed dims contain $clog2()
#2578 opened Aug 18, 2026 by kbrunham-intel Contributor Loading…
2 of 3 tasks
1
1
Fix formatter spacing around path separators in macro arguments
#2577 opened Aug 18, 2026 by kbrunham-intel Contributor Loading…
2 of 3 tasks
1
1
Fix formatter non-convergence for multi-line macro sums
#2548 opened Jul 17, 2026 by kbrunham-intel Contributor Loading…
3 of 4 tasks
1
6
Fix formatter abort on line-continuation before aligned ports
#2546 opened Jul 17, 2026 by kbrunham-intel Contributor Loading…
2 of 3 tasks
1
4
Fix formatter lexical mismatch for macros at end of line
#2545 opened Jul 17, 2026 by kbrunham-intel Contributor Loading…
2 of 3 tasks
1
7
Fix formatter non-convergence for continuation EOL comments
#2543 opened Jul 17, 2026 by kbrunham-intel Contributor Loading…
2 of 3 tasks
1
6
[preprocessor] Fix crash/hang on truncated callable macro invocation
#2535 opened Jul 9, 2026 by EylonKrause Contributor Loading…
2
port-name-suffix: handle ref direction and all-underscore names
#2534 opened Jul 6, 2026 by EylonKrause Contributor Loading…
5
preprocessor: stop macro-argument scan on an unexpected/EOF token
#2532 opened Jul 5, 2026 by EylonKrause Contributor Loading…
4
Use flex and bison directly instead from toolchain.
#2524 opened Jun 16, 2026 by hzeller Collaborator Loading…
1
7
Fix module-level alignment breaking after non-alignable constructs
#2500 opened Mar 27, 2026 by dannyoler Loading…
3 tasks
2
fix issue 2288: add --rules=+generate-label-prefix=prefix:A_ to change the style_regex
#2498 opened Mar 21, 2026 by ddppt-yy Loading…
1
3
Modernize use of bison and flex in a more elaborate rule.
#2497 opened Mar 17, 2026 by hzeller Collaborator • Draft
1
Added support for token concatenation
#2488 opened Jan 21, 2026 by sifferman Loading…
1
Add inlay hint support for Verilog module instantiations
#2487 opened Jan 18, 2026 by ya-uhs Loading…
1
Add TextMate Grammar for Verilog/SystemVerilog Highlighting
#2472 opened Nov 25, 2025 by clysto Loading…
7
Update bison.bzl and flex.bzl to work with Bazel 8
#2452 opened Aug 29, 2025 by mneilly Loading…
6
Disable --//bazel:use_local_flex_bison that won't work with bazel 8
#2449 opened Aug 26, 2025 by hzeller Collaborator • Draft
1
Resolve "Non ANSI-C style input,output port declaration Verilog code linter issue"
#2447 opened Aug 22, 2025 by matlupi • Draft
5
Simplify settings of warnings.
#2386 opened Apr 7, 2025 by hzeller Collaborator • Draft
Add VSCode command of generating verible.filelist at the root folder
#2277 opened Oct 5, 2024 by Hamster5295 Loading…
3
Resolve "Rejected valid signal name"
#2102 opened Feb 6, 2024 by matlupi Loading…
1
6
Enable suspicious-semicolon_rule by default
#2066 opened Dec 21, 2023 by IEncinas10 Collaborator Loading…
2
ProTip! Adding no:label will show everything without a label.