Preprocessor Imports Macros Incorrectly

[zacaric]

Describe the bug

This had to do with the preprocessor (wasn't sure what issue template to use). When using the preprocessor to create a pre-processed file that includes information from a *.svh file, instead of importing as `define MACRO it is importing it as `defineMACRO, missing the space between `define and MACRO.

This is with version v0.0-4023-gc1271a00

This was found when linting a test bench that uses SVUnit for unit testing with the integrated clock generator macro in SVUnit.

Test case (preferably reduced)

Command Ran
verible-verilog-preprocessor preprocess +incdir+svunit/svunit-3.38.0/svunit_base add_unit_test.sv

svunit_defines.svh

`ifndef FAIL_UNLESS_EQUAL
`define FAIL_UNLESS_EQUAL(a,b) \
  begin \
    if (svunit_pkg::current_tc.fail(`"fail_unless_equal`", ((a)!==(b)), `"(a) !== (b)`", `__FILE__, `__LINE__)) begin \
      if (svunit_pkg::current_tc.is_running()) svunit_pkg::current_tc.give_up(); \
    end \
  end
`endif

`define SVUNIT_TESTS_BEGIN \
  task automatic run(); \
    svunit_ut.run(); \
  endtask \
  \
  svunit_pkg::svunit_test __tests[$]; \

`define SVUNIT_TESTS_END \
  function void __register_tests(); \
    foreach (__tests[i]) \
      svunit_ut.add_test(__tests[i]); \
  endfunction

`define SVTEST(_NAME_) \
  typedef class _NAME_; \
  \
  bit __is_``_NAME_``_registered = __register_``_NAME_``(); \
  function automatic bit __register_``_NAME_``(); \
    _NAME_ test = new(); \
    __tests.push_back(test); \
    return 1; \
  endfunction \
  \
  class _NAME_ extends svunit_pkg::svunit_test; \
    \
    function new(); \
      super.new(`__svunit_stringify(_NAME_)); \
    endfunction \
    \
    virtual task run(); \
      fork \
        SVTEST_``_NAME_``(); \
        `SVUNIT_FUSE \
      join_any \
    endtask \
    \
    virtual task unit_test_setup(); \
      setup(); \
    endtask \
    \
    virtual task unit_test_teardown(); \
      teardown(); \
    endtask \
    \
  endclass \
  \
  task automatic SVTEST_``_NAME_``();

`define SVTEST_END \
  endtask

`define SVUNIT_FUSE \
`ifdef SVUNIT_TIMEOUT \
begin \
  bit svunit_timeout = 1; \
  #(`SVUNIT_TIMEOUT); \
  `FAIL_IF(svunit_timeout) \
end \
`endif

`define SVUNIT_CLK_GEN(_clk_variable, _half_period) \
    initial begin \
        _clk_variable = 0; \
        wait(svunit_ut != null); \
        forever begin \
            if( svunit_ut.is_running() ) \
                #_half_period _clk_variable = !_clk_variable; \
            else \
                svunit_ut.__wait_until_started(); \
        end \
    end

add_unit_test.sv

`include "svunit_defines.svh"

module add_unit_test;
    import svunit_pkg::svunit_testcase;

    string name = "add_ut";
    svunit_testcase svunit_ut;

    localparam DWIDTH = 8;
    localparam CLK_PERIOD = 10;
    localparam ITERATIONS = 5;
    localparam SYSTEM_DELAY = 2;
    localparam OFFSET = 7;
    localparam SCALAR_VALUE = 36;
    localparam RESET_CYCLES = 2;

    logic clk, resetn, overflow;
    logic [DWIDTH-1:0] a, b;
    logic [DWIDTH-1:0] sum;
    add #(
        .DWIDTH(DWIDTH)
    ) my_add (
        .clk(clk),
        .resetn(resetn),
        .a(a),
        .b(b),
        .sum(sum),
        .overflow(overflow)
    );

    function void build();
        svunit_ut = new(name);
    endfunction

    task setup();
        svunit_ut.setup();
        /* Place Setup Code Here */
        resetn = 1;
        clk = 1;
        a = {DWIDTH{1'bx}};
        b = {DWIDTH{1'bx}};
    endtask

    task teardown();
        svunit_ut.teardown();
    endtask

    task reset();
        resetn = 1;
        @(posedge clk);
        resetn = 0;
        repeat(RESET_CYCLES) @(posedge clk);
        resetn = 1;
    endtask

    function logic [DWIDTH-1:0] summation (logic [DWIDTH-1:0] a,b);
        summation = a+b;
    endfunction

    `SVUNIT_CLK_GEN(clk, (CLK_PERIOD/2))

    `SVUNIT_TESTS_BEGIN

    `SVTEST(reset_test)
        // Should start off as unknown
        `FAIL_UNLESS_EQUAL(sum, {DWIDTH{1'bx}}) 
        repeat(SYSTEM_DELAY) @(posedge clk);
        reset();
        `FAIL_UNLESS_EQUAL(sum, {DWIDTH{1'b0}})
    `SVTEST_END

    `SVTEST(core_function)
        repeat(1) begin
            a = $urandom_range(0, (1<<DWIDTH)-1);
            b = $urandom_range(0, (1<<DWIDTH)-1);
            repeat(SYSTEM_DELAY) @(posedge clk);
            $display("%d : %d", summation(a,b), sum);
            `FAIL_UNLESS_EQUAL(sum, summation(a,b))
        end
    `SVTEST_END

    `SVUNIT_TESTS_END

endmodule

Actual vs. expected behavior

See bug description.