verible-verilog-format crash for special wire signed vectors

[frazezhang]

Test case

module myModule (
    myinput
);
input wire signed [7:0] myInput;
endmodule

Include any options or configuration used.

Actual output

F1201 16:31:46.868525   31602 tree-unwrapper.cc:3195] Check failed: NextUnfilteredToken()->text().begin() == leaf.get().text().begin() 
[symbolize_elf.inc : 392] RAW: Unable to get high fd: rc=-1, limit=0

This should be an legal syntax can be accepted by VCS and Verdi.