Verible Fails to Parse Non-ANSI Verilog Port Syntax

[gmCAD]

Description

Verible reports a syntax error when parsing modules that use Non-ANSI Verilog port declarations.

Example of Failing Code

module test(a);

input var real a;

endmodule

Error Message

test.sv:3:7-9: syntax error at token "var"

ANSI Version (Parses Successfully):

module test(input var real a);
endmodule

Actual behavior:

Valid Non-ANSI code is rejected with a syntax error.

Verible Version

• Verible Version : (v0.0-3933)