Hi,
verilog code obfuscation is widely adopted during IP delivery in the industry, and verible-verilog-obfuscate works well on code obfuscation. However, it should gives more fine control to make it more flexible.
- Obfuscate should keep top level module name and port name by default to allow following compile/sim flow run smoothly.
- Some vital signals like clock/reset should be preserved in case some workflow depend on these name.
- give control on preserve instance name and module name to make it easier during backend P&R flow.