Skip to content

Verible-verilog format fails when a wrapped assign has a multiline comment #2542

Description

@kbrunham-intel

verible-verilog-format fails the convergence check when a wrapped assign has a multi-line EOL comment after the statement. The first format pass column-aligns the continuation comment far to the right; re-formatting left-aligns it. So format(format(x)) != format(x).

This is not the same as #2540 (end / EOL comment / else if).

Test case

module m;
  assign status_ur = !(status_sc || status_ca ||
    status_crs);      // Completions with a Reserved Completion
                      // Status value are treated as UR
endmodule

Include any options or configuration used.

Actual output

Re-formatted text does not match formatted text; formatting failed to converge!  Please file a bug.

Metadata

Metadata

Assignees

No one assigned

    Labels

    formatterVerilog code formatter issues

    Type

    No type

    Projects

    No projects

    Milestone

    No milestone

    Relationships

    None yet

    Development

    No branches or pull requests

    Issue actions