Formatter: lexical mismatch (MacroIdentifier vs MacroIdItem) when wrapping puts a macro at end of line #2544

verible-verilog-format can rewrite a $bits(...)'(...) cast so a `MACRO ends a line. Re-lexing that output classifies the macro as MacroIdItem instead of MacroIdentifier, so verification reports a lexical difference even though the text looks equivalent.

Test case

module m;
  assign result_value = $bits(result_value)'( compare_bytes(input_data[DATA_WIDTH_INT-1:0], input_datak[STROBE_WIDTH_INT-1:0], `TOKEN_BYTE) );
endmodule

Include any options or configuration used.

Actual output

Formatted output is lexically different from the input.    Please file a bug.  Details:
Mismatched token enums.  got: (MacroIdentifier) (#296: "`TOKEN_BYTE") vs. (MacroIdItem) (#298: "`TOKEN_BYTE")