Verible 4071 fails with an assertion when formatting.
verible-verilog-format hits a fatal CHECK in align.h during tabular alignment of module ports when a // comment line ends with a trailing \ (Verilog line-continuation) immediately before the first port.
Test case
Important: the comment line must end with a single backslash () before the newline.
module m (
//\
input a
,input b
);
endmodule
Actual output
F0717 07:13:36.078103 19024 align.h:423] Check failed: leading_tokens.empty() || first_tree_token_it == ftokens.end() || first_tree_token_it->before.break_decision != SpacingOptions::kMustWrap
*** Check failure stack trace: ***
@ 0x431365 verible::ScanPartitionForAlignmentCells_WithNonTreeTokens<>()
@ 0x4313c3 std::_Function_handler<>::_M_invoke()
@ 0x45f1f9 verible::AlignablePartitionGroup::CalculateAlignmentSpacings()
@ 0x461306 verible::AlignablePartitionGroup::Align()
@ 0x46160e verible::TabularAlignTokens()
@ 0x43470c verilog::formatter::TabularAlignTokenPartitions()
@ 0x41f31f verible::ApplyPreOrder<>()
@ 0x423488 verilog::formatter::Formatter::Format()
@ 0x424be1 verilog::formatter::FormatVerilog()
@ 0x42523b verilog::formatter::FormatVerilog()
@ 0x40f10c main
@ 0x57cdb8 __libc_start_call_main
@ 0x57ef80 __libc_start_main_impl
@ 0x410e65 _start
*** SIGABRT received at time=1784297616 on cpu 40 ***
PC: @ 0x5b4b4c (unknown) pthread_kill
@ 0x5959e0 (unknown) (unknown)
@ 0x59595e 32 gsignal
@ 0x40e1d5 192 abort
@ 0x4dd786 16 absl::lts_20260107::log_internal::LogMessage::FailWithoutStackTrace()
@ 0x4ddc5c 32 absl::lts_20260107::log_internal::LogMessage::Die()
@ 0x4ddcf1 32 absl::lts_20260107::log_internal::LogMessage::SendToLog()
@ 0x431365 304 verible::ScanPartitionForAlignmentCells_WithNonTreeTokens<>()
@ 0x4313c3 32 std::_Function_handler<>::_M_invoke()
@ 0x45f1f9 848 verible::AlignablePartitionGroup::CalculateAlignmentSpacings()
@ 0x461306 208 verible::AlignablePartitionGroup::Align()
@ 0x46160e 160 verible::TabularAlignTokens()
@ 0x43470c 1024 verilog::formatter::TabularAlignTokenPartitions()
@ 0x41f31f 176 verible::ApplyPreOrder<>()
@ 0x423488 1088 verilog::formatter::Formatter::Format()
@ 0x424be1 720 verilog::formatter::FormatVerilog()
@ 0x42523b 880 verilog::formatter::FormatVerilog()
@ 0x40f10c 992 main
@ 0x57cdb8 160 __libc_start_call_main
@ 0x57ef80 80 __libc_start_main_impl
@ 0x410e65 (unknown) _start
Verible 4071 fails with an assertion when formatting.
verible-verilog-format hits a fatal CHECK in align.h during tabular alignment of module ports when a // comment line ends with a trailing \ (Verilog line-continuation) immediately before the first port.
Test case
Important: the comment line must end with a single backslash () before the newline.
Actual output