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Add CPUID for AvxVnniInt8 and AvxVnniInt16 #113956

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Add CPUID for AvxVnniInt8 and AvxVnniInt16 #113956

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2 changes: 2 additions & 0 deletions src/coreclr/inc/clrconfigvalues.h
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Original file line number Diff line number Diff line change
Expand Up @@ -725,6 +725,8 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX512VBMI_VL, W("EnableAVX512V
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX10v1, W("EnableAVX10v1"), 1, "Allows AVX10v1+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX10v2, W("EnableAVX10v2"), 0, "Allows AVX10v2+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVXVNNI, W("EnableAVXVNNI"), 1, "Allows AVXVNNI+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVXVNNIINT8, W("EnableAVXVNNIINT8"), 1, "Allows AVXVNNI+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVXVNNIINT16, W("EnableAVXVNNIINT16"), 1, "Allows AVXVNNI+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableBMI1, W("EnableBMI1"), 1, "Allows BMI1+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableBMI2, W("EnableBMI2"), 1, "Allows BMI2+ hardware intrinsics to be disabled")
RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableFMA, W("EnableFMA"), 1, "Allows FMA+ hardware intrinsics to be disabled")
Expand Down
180 changes: 124 additions & 56 deletions src/coreclr/inc/corinfoinstructionset.h
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Original file line number Diff line number Diff line change
Expand Up @@ -94,34 +94,40 @@ enum CORINFO_InstructionSet
InstructionSet_GFNI=44,
InstructionSet_GFNI_V256=45,
InstructionSet_GFNI_V512=46,
InstructionSet_X86Base_X64=47,
InstructionSet_SSE_X64=48,
InstructionSet_SSE2_X64=49,
InstructionSet_SSE3_X64=50,
InstructionSet_SSSE3_X64=51,
InstructionSet_SSE41_X64=52,
InstructionSet_SSE42_X64=53,
InstructionSet_AVX_X64=54,
InstructionSet_AVX2_X64=55,
InstructionSet_AES_X64=56,
InstructionSet_BMI1_X64=57,
InstructionSet_BMI2_X64=58,
InstructionSet_FMA_X64=59,
InstructionSet_LZCNT_X64=60,
InstructionSet_PCLMULQDQ_X64=61,
InstructionSet_POPCNT_X64=62,
InstructionSet_AVXVNNI_X64=63,
InstructionSet_X86Serialize_X64=64,
InstructionSet_AVX512F_X64=65,
InstructionSet_AVX512BW_X64=66,
InstructionSet_AVX512CD_X64=67,
InstructionSet_AVX512DQ_X64=68,
InstructionSet_AVX512VBMI_X64=69,
InstructionSet_AVX10v1_X64=70,
InstructionSet_AVX10v1_V512_X64=71,
InstructionSet_AVX10v2_X64=72,
InstructionSet_AVX10v2_V512_X64=73,
InstructionSet_GFNI_X64=74,
InstructionSet_AVXVNNIINT8=47,
InstructionSet_AVXVNNIINT8_V512=48,
InstructionSet_AVXVNNIINT16=49,
InstructionSet_AVXVNNIINT16_V512=50,
InstructionSet_X86Base_X64=51,
InstructionSet_SSE_X64=52,
InstructionSet_SSE2_X64=53,
InstructionSet_SSE3_X64=54,
InstructionSet_SSSE3_X64=55,
InstructionSet_SSE41_X64=56,
InstructionSet_SSE42_X64=57,
InstructionSet_AVX_X64=58,
InstructionSet_AVX2_X64=59,
InstructionSet_AES_X64=60,
InstructionSet_BMI1_X64=61,
InstructionSet_BMI2_X64=62,
InstructionSet_FMA_X64=63,
InstructionSet_LZCNT_X64=64,
InstructionSet_PCLMULQDQ_X64=65,
InstructionSet_POPCNT_X64=66,
InstructionSet_AVXVNNI_X64=67,
InstructionSet_X86Serialize_X64=68,
InstructionSet_AVX512F_X64=69,
InstructionSet_AVX512BW_X64=70,
InstructionSet_AVX512CD_X64=71,
InstructionSet_AVX512DQ_X64=72,
InstructionSet_AVX512VBMI_X64=73,
InstructionSet_AVX10v1_X64=74,
InstructionSet_AVX10v1_V512_X64=75,
InstructionSet_AVX10v2_X64=76,
InstructionSet_AVX10v2_V512_X64=77,
InstructionSet_GFNI_X64=78,
InstructionSet_AVXVNNIINT8_X64=79,
InstructionSet_AVXVNNIINT16_X64=80,
#endif // TARGET_AMD64
#ifdef TARGET_X86
InstructionSet_X86Base=1,
Expand Down Expand Up @@ -170,34 +176,40 @@ enum CORINFO_InstructionSet
InstructionSet_GFNI=44,
InstructionSet_GFNI_V256=45,
InstructionSet_GFNI_V512=46,
InstructionSet_X86Base_X64=47,
InstructionSet_SSE_X64=48,
InstructionSet_SSE2_X64=49,
InstructionSet_SSE3_X64=50,
InstructionSet_SSSE3_X64=51,
InstructionSet_SSE41_X64=52,
InstructionSet_SSE42_X64=53,
InstructionSet_AVX_X64=54,
InstructionSet_AVX2_X64=55,
InstructionSet_AES_X64=56,
InstructionSet_BMI1_X64=57,
InstructionSet_BMI2_X64=58,
InstructionSet_FMA_X64=59,
InstructionSet_LZCNT_X64=60,
InstructionSet_PCLMULQDQ_X64=61,
InstructionSet_POPCNT_X64=62,
InstructionSet_AVXVNNI_X64=63,
InstructionSet_X86Serialize_X64=64,
InstructionSet_AVX512F_X64=65,
InstructionSet_AVX512BW_X64=66,
InstructionSet_AVX512CD_X64=67,
InstructionSet_AVX512DQ_X64=68,
InstructionSet_AVX512VBMI_X64=69,
InstructionSet_AVX10v1_X64=70,
InstructionSet_AVX10v1_V512_X64=71,
InstructionSet_AVX10v2_X64=72,
InstructionSet_AVX10v2_V512_X64=73,
InstructionSet_GFNI_X64=74,
InstructionSet_AVXVNNIINT8=47,
InstructionSet_AVXVNNIINT8_V512=48,
InstructionSet_AVXVNNIINT16=49,
InstructionSet_AVXVNNIINT16_V512=50,
InstructionSet_X86Base_X64=51,
InstructionSet_SSE_X64=52,
InstructionSet_SSE2_X64=53,
InstructionSet_SSE3_X64=54,
InstructionSet_SSSE3_X64=55,
InstructionSet_SSE41_X64=56,
InstructionSet_SSE42_X64=57,
InstructionSet_AVX_X64=58,
InstructionSet_AVX2_X64=59,
InstructionSet_AES_X64=60,
InstructionSet_BMI1_X64=61,
InstructionSet_BMI2_X64=62,
InstructionSet_FMA_X64=63,
InstructionSet_LZCNT_X64=64,
InstructionSet_PCLMULQDQ_X64=65,
InstructionSet_POPCNT_X64=66,
InstructionSet_AVXVNNI_X64=67,
InstructionSet_X86Serialize_X64=68,
InstructionSet_AVX512F_X64=69,
InstructionSet_AVX512BW_X64=70,
InstructionSet_AVX512CD_X64=71,
InstructionSet_AVX512DQ_X64=72,
InstructionSet_AVX512VBMI_X64=73,
InstructionSet_AVX10v1_X64=74,
InstructionSet_AVX10v1_V512_X64=75,
InstructionSet_AVX10v2_X64=76,
InstructionSet_AVX10v2_V512_X64=77,
InstructionSet_GFNI_X64=78,
InstructionSet_AVXVNNIINT8_X64=79,
InstructionSet_AVXVNNIINT16_X64=80,
#endif // TARGET_X86

};
Expand Down Expand Up @@ -371,6 +383,10 @@ struct CORINFO_InstructionSetFlags
AddInstructionSet(InstructionSet_AVX10v2_V512_X64);
if (HasInstructionSet(InstructionSet_GFNI))
AddInstructionSet(InstructionSet_GFNI_X64);
if (HasInstructionSet(InstructionSet_AVXVNNIINT8))
AddInstructionSet(InstructionSet_AVXVNNIINT8_X64);
if (HasInstructionSet(InstructionSet_AVXVNNIINT16))
AddInstructionSet(InstructionSet_AVXVNNIINT16_X64);
#endif // TARGET_AMD64
#ifdef TARGET_X86
#endif // TARGET_X86
Expand Down Expand Up @@ -569,6 +585,14 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_GFNI);
if (resultflags.HasInstructionSet(InstructionSet_GFNI_X64) && !resultflags.HasInstructionSet(InstructionSet_GFNI))
resultflags.RemoveInstructionSet(InstructionSet_GFNI_X64);
if (resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8_X64))
resultflags.RemoveInstructionSet(InstructionSet_AVXVNNIINT8);
if (resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8_X64) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8))
resultflags.RemoveInstructionSet(InstructionSet_AVXVNNIINT8_X64);
if (resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16_X64))
resultflags.RemoveInstructionSet(InstructionSet_AVXVNNIINT16);
if (resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16_X64) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16))
resultflags.RemoveInstructionSet(InstructionSet_AVXVNNIINT16_X64);
if (resultflags.HasInstructionSet(InstructionSet_SSE) && !resultflags.HasInstructionSet(InstructionSet_X86Base))
resultflags.RemoveInstructionSet(InstructionSet_SSE);
if (resultflags.HasInstructionSet(InstructionSet_SSE2) && !resultflags.HasInstructionSet(InstructionSet_SSE))
Expand Down Expand Up @@ -683,6 +707,14 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8_V512))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16_V512))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512);
if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_SSE))
resultflags.RemoveInstructionSet(InstructionSet_Vector128);
if (resultflags.HasInstructionSet(InstructionSet_Vector256) && !resultflags.HasInstructionSet(InstructionSet_AVX))
Expand Down Expand Up @@ -811,6 +843,14 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVX10v1_V512))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT8_V512))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512);
if (resultflags.HasInstructionSet(InstructionSet_AVX10v2_V512) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNIINT16_V512))
resultflags.RemoveInstructionSet(InstructionSet_AVX10v2_V512);
if (resultflags.HasInstructionSet(InstructionSet_Vector128) && !resultflags.HasInstructionSet(InstructionSet_SSE))
resultflags.RemoveInstructionSet(InstructionSet_Vector128);
if (resultflags.HasInstructionSet(InstructionSet_Vector256) && !resultflags.HasInstructionSet(InstructionSet_AVX))
Expand Down Expand Up @@ -1047,6 +1087,18 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
return "GFNI_V256";
case InstructionSet_GFNI_V512 :
return "GFNI_V512";
case InstructionSet_AVXVNNIINT8 :
return "AVXVNNIINT8";
case InstructionSet_AVXVNNIINT8_X64 :
return "AVXVNNIINT8_X64";
case InstructionSet_AVXVNNIINT8_V512 :
return "AVXVNNIINT8_V512";
case InstructionSet_AVXVNNIINT16 :
return "AVXVNNIINT16";
case InstructionSet_AVXVNNIINT16_X64 :
return "AVXVNNIINT16_X64";
case InstructionSet_AVXVNNIINT16_V512 :
return "AVXVNNIINT16_V512";
#endif // TARGET_AMD64
#ifdef TARGET_X86
case InstructionSet_X86Base :
Expand Down Expand Up @@ -1141,6 +1193,14 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
return "GFNI_V256";
case InstructionSet_GFNI_V512 :
return "GFNI_V512";
case InstructionSet_AVXVNNIINT8 :
return "AVXVNNIINT8";
case InstructionSet_AVXVNNIINT8_V512 :
return "AVXVNNIINT8_V512";
case InstructionSet_AVXVNNIINT16 :
return "AVXVNNIINT16";
case InstructionSet_AVXVNNIINT16_V512 :
return "AVXVNNIINT16_V512";
#endif // TARGET_X86

default:
Expand Down Expand Up @@ -1224,6 +1284,10 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
case READYTORUN_INSTRUCTION_Gfni: return InstructionSet_GFNI;
case READYTORUN_INSTRUCTION_Gfni_V256: return InstructionSet_GFNI_V256;
case READYTORUN_INSTRUCTION_Gfni_V512: return InstructionSet_GFNI_V512;
case READYTORUN_INSTRUCTION_AvxVnniInt8: return InstructionSet_AVXVNNIINT8;
case READYTORUN_INSTRUCTION_AvxVnniInt8_V512: return InstructionSet_AVXVNNIINT8_V512;
case READYTORUN_INSTRUCTION_AvxVnniInt16: return InstructionSet_AVXVNNIINT16;
case READYTORUN_INSTRUCTION_AvxVnniInt16_V512: return InstructionSet_AVXVNNIINT16_V512;
#endif // TARGET_AMD64
#ifdef TARGET_X86
case READYTORUN_INSTRUCTION_X86Base: return InstructionSet_X86Base;
Expand Down Expand Up @@ -1269,6 +1333,10 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
case READYTORUN_INSTRUCTION_Gfni: return InstructionSet_GFNI;
case READYTORUN_INSTRUCTION_Gfni_V256: return InstructionSet_GFNI_V256;
case READYTORUN_INSTRUCTION_Gfni_V512: return InstructionSet_GFNI_V512;
case READYTORUN_INSTRUCTION_AvxVnniInt8: return InstructionSet_AVXVNNIINT8;
case READYTORUN_INSTRUCTION_AvxVnniInt8_V512: return InstructionSet_AVXVNNIINT8_V512;
case READYTORUN_INSTRUCTION_AvxVnniInt16: return InstructionSet_AVXVNNIINT16;
case READYTORUN_INSTRUCTION_AvxVnniInt16_V512: return InstructionSet_AVXVNNIINT16_V512;
#endif // TARGET_X86

default:
Expand Down
10 changes: 5 additions & 5 deletions src/coreclr/inc/jiteeversionguid.h
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Expand Up @@ -37,11 +37,11 @@

#include <minipal/guid.h>

constexpr GUID JITEEVersionIdentifier = { /* 7139df75-63b2-4610-9a53-f9a86f474db8 */
0x7139df75,
0x63b2,
0x4610,
{0x9a, 0x53, 0xf9, 0xa8, 0x6f, 0x47, 0x4d, 0xb8}
constexpr GUID JITEEVersionIdentifier = { /* 16edf70b-d4d0-44c5-9ebc-a9d6898119a5 */
0x16edf70b,
0xd4d0,
0x44c5,
{0x9e, 0xbc, 0xa9, 0xd6, 0x89, 0x81, 0x19, 0xa5}
};

#endif // JIT_EE_VERSIONING_GUID_H
4 changes: 4 additions & 0 deletions src/coreclr/inc/readytoruninstructionset.h
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Expand Up @@ -66,6 +66,10 @@ enum ReadyToRunInstructionSet
READYTORUN_INSTRUCTION_RiscV64Base=56,
READYTORUN_INSTRUCTION_Zba=57,
READYTORUN_INSTRUCTION_Zbb=58,
READYTORUN_INSTRUCTION_AvxVnniInt8=59,
READYTORUN_INSTRUCTION_AvxVnniInt8_V512=60,
READYTORUN_INSTRUCTION_AvxVnniInt16=61,
READYTORUN_INSTRUCTION_AvxVnniInt16_V512=62,

};

Expand Down
6 changes: 6 additions & 0 deletions src/coreclr/jit/hwintrinsic.cpp
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Expand Up @@ -812,6 +812,10 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = {
{ FIRST_NI_GFNI, LAST_NI_GFNI },
{ FIRST_NI_GFNI_V256, LAST_NI_GFNI_V256 },
{ FIRST_NI_GFNI_V512, LAST_NI_GFNI_V512 },
{ NI_Illegal, NI_Illegal }, // AVXVNNIINT8
{ NI_Illegal, NI_Illegal }, // AVXVNNIINT8_V512
{ NI_Illegal, NI_Illegal }, // AVXVNNIINT16
{ NI_Illegal, NI_Illegal }, // AVXVNNIINT16_V512
Comment on lines +815 to +818
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Any reason we're not adding the APIs at the same time? They look like they should be generally table driven, so it should be a minimal change on top...

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We can do that too. For all other ISAs, we generally did CPUID and API introduction as separate PRs. Also, it becomes easier to run superpmi once the CPUID PR goes in. Let me know what you'd prefer.

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For all other ISAs, we generally did CPUID and API introduction as separate PRs.

For some of the others, like AVX10.2, we've done it incrementally because of the number of APIs and total work required.

That is, checking in the CPUID support first allowed a reduction of conflicts and parallelization of adding a large number of intrinsic APIs across several PRs.

In this case, there's only a very small number of APIs that are likely entirely table driven, so there's little to no risk of conflicts or additional churn.

Doing it all at once lets us build confidence the CPUID checks and end to end story is correct since it is self contained like that and since it allows adding the CPUID and other tests at the same time.

Also, it becomes easier to run superpmi once the CPUID PR goes in

There's not much need to run SPMI for net new intrinsics that nothing is using yet, we're going to get zero diffs.

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Ohkay. Thanks for the review. I will switch this PR to add everything together and then update you.

{ FIRST_NI_X86Base_X64, LAST_NI_X86Base_X64 },
{ FIRST_NI_SSE_X64, LAST_NI_SSE_X64 },
{ FIRST_NI_SSE2_X64, LAST_NI_SSE2_X64 },
Expand Down Expand Up @@ -840,6 +844,8 @@ static const HWIntrinsicIsaRange hwintrinsicIsaRangeArray[] = {
{ NI_Illegal, NI_Illegal }, // AVX10v2_X64
{ NI_Illegal, NI_Illegal }, // AVX10v2_V512_X64
{ NI_Illegal, NI_Illegal }, // GFNI_X64
{ NI_Illegal, NI_Illegal }, // AVXVNNIINT8_X64
{ NI_Illegal, NI_Illegal }, // AVXVNNIINT16_X64
#elif defined (TARGET_ARM64)
{ FIRST_NI_ArmBase, LAST_NI_ArmBase },
{ FIRST_NI_AdvSimd, LAST_NI_AdvSimd },
Expand Down
2 changes: 2 additions & 0 deletions src/coreclr/jit/jitconfigvalues.h
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Expand Up @@ -411,6 +411,8 @@ RELEASE_CONFIG_INTEGER(EnableAVX512VBMI_VL, "EnableAVX512VBMI_VL",
RELEASE_CONFIG_INTEGER(EnableAVX10v1, "EnableAVX10v1", 1) // Allows AVX10v1+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableAVX10v2, "EnableAVX10v2", 1) // Allows AVX10v2+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableAVXVNNI, "EnableAVXVNNI", 1) // Allows AVXVNNI+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableAVXVNNIINT8, "EnableAVXVNNIINT8", 1) // Allows AVXVNNI+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableAVXVNNIINT16, "EnableAVXVNNIINT16", 1) // Allows AVXVNNI+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableBMI1, "EnableBMI1", 1) // Allows BMI1+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableBMI2, "EnableBMI2", 1) // Allows BMI2+ hardware intrinsics to be disabled
RELEASE_CONFIG_INTEGER(EnableFMA, "EnableFMA", 1) // Allows FMA+ hardware intrinsics to be disabled
Expand Down
16 changes: 16 additions & 0 deletions src/coreclr/tools/Common/Compiler/HardwareIntrinsicHelpers.cs
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Expand Up @@ -85,6 +85,8 @@ private static class XArchIntrinsicConstants
public const int Vpclmulqdq = 0x200000;
public const int Avx10v2 = 0x400000;
public const int Gfni = 0x800000;
public const int AvxVnniInt8 = 0x1000000;
public const int AvxVnniInt16 = 0x2000000;

public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags)
{
Expand Down Expand Up @@ -154,6 +156,14 @@ public static void AddToBuilder(InstructionSetSupportBuilder builder, int flags)
builder.AddSupportedInstructionSet("avx10v2");
if (((flags & Avx10v2) != 0) && ((flags & Avx512) != 0))
builder.AddSupportedInstructionSet("avx10v2_v512");
if ((flags & AvxVnniInt8) != 0)
builder.AddSupportedInstructionSet("avxvnniint8");
if (((flags & AvxVnniInt8) != 0) && ((flags & Avx512) != 0))
builder.AddSupportedInstructionSet("avxvnniint8_v512");
if ((flags & AvxVnniInt16) != 0)
builder.AddSupportedInstructionSet("avxvnniint16");
if (((flags & AvxVnniInt16) != 0) && ((flags & Avx512) != 0))
builder.AddSupportedInstructionSet("avxvnniint16_v512");
if ((flags & Gfni) != 0)
{
builder.AddSupportedInstructionSet("gfni");
Expand Down Expand Up @@ -235,6 +245,12 @@ public static int FromInstructionSet(InstructionSet instructionSet)
InstructionSet.X64_GFNI_X64 => Gfni,
InstructionSet.X64_GFNI_V256 => (Gfni | Avx),
InstructionSet.X64_GFNI_V512 => (Gfni | Avx512),
InstructionSet.X64_AVXVNNIINT8 => AvxVnniInt8,
InstructionSet.X64_AVXVNNIINT8_X64 => AvxVnniInt8,
InstructionSet.X64_AVXVNNIINT8_V512 => (AvxVnniInt8 | Avx512),
InstructionSet.X64_AVXVNNIINT16 => AvxVnniInt16,
InstructionSet.X64_AVXVNNIINT16_X64 => AvxVnniInt16,
InstructionSet.X64_AVXVNNIINT16_V512 => (AvxVnniInt16 | Avx512),

// Baseline ISAs - they're always available
InstructionSet.X64_SSE => 0,
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