Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

[RISC-V] Fused multiply-add #113961

Draft
wants to merge 7 commits into
base: main
Choose a base branch
from
Draft

Conversation

tomeksowi
Copy link
Contributor

Part of #84834, cc @dotnet/samsung

@dotnet-issue-labeler dotnet-issue-labeler bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Mar 27, 2025
@dotnet-policy-service dotnet-policy-service bot added the community-contribution Indicates that the PR has been added by a community member label Mar 27, 2025
Comment on lines 69 to 74
target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE FEATURE_SIMD)
target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE FEATURE_HW_INTRINSICS)
target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE FEATURE_MASKED_HW_INTRINSICS)
elseif (TARGETDETAILS_ARCH STREQUAL "riscv64")
target_compile_definitions(${TARGETDETAILS_TARGET} PRIVATE FEATURE_HW_INTRINSICS)
endif ()
Copy link
Contributor Author

@tomeksowi tomeksowi Mar 27, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I'm still hesitating whether separating FEATURE_HW_INTRINSICS from SIMD and MASKED_HW_INTRINSICS is the right approach, there's been little code separation between them. Until we bring up the "V" extension the intrinsics RISC-V needs are scalar (e.g. FusedMultiplyAdd, LeadingZeroCount, PopCount, MultiplyHigh) and usually covered in common CoreLib parts like System.Math.

An alternative would be to handle them like #113689 and fix the value numbering for 3-operand GT_INTRINSIC to get FMA:

// TODO-CQ-XArch: Ideally we would create a GT_INTRINSIC node for fma, however, that currently
// requires more extensive changes to valuenum to support methods with 3 operands
// We want to generate a GT_INTRINSIC node in the case the call can't be treated as
// a target intrinsic so that we can still benefit from CSE and constant folding.

Not sure if changes would be less extensive than maintaining the above mentioned separation.

@dotnet/jit-contrib @jakobbotsch if you have an opinion.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

LeadingZeroCount and friends look doable via GT_INTRINSIC (WiP). So that leaves us with FMA as the odd one out.

Copy link
Contributor

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

@risc-vv
Copy link

risc-vv commented Mar 27, 2025

RISC-V Release-CLR-VF2: 9527 / 9547 (99.79%)
=======================
      passed: 9527
      failed: 3
     skipped: 106
      killed: 17
------------------------
  TOTAL libs: 9653
 TOTAL tests: 9653
   REAL time: 2h 9min 24s 590ms
=======================

Release-CLR-VF2.md, Release-CLR-VF2.xml, testclr_output.tar.gz

Build information and commands

GIT: c2bce30724f34ac65c8d4018925108b3c2c1ae8f
CI: a8426a46d8575dfcb3b5fec0d7d0b7a7c118d690
REPO: tomeksowi/runtime
BRANCH: hw-intrinsics
CONFIG: Release
LIB_CONFIG: Release

RISC-V Release-FX-VF2: 423645 / 458893 (92.32%)
=======================
      passed: 423645
      failed: 678
     skipped: 1482
      killed: 34570
------------------------
  TOTAL libs: 258
 TOTAL tests: 460375
   REAL time: 2h 54min 23s 395ms
=======================

Release-FX-VF2.md, Release-FX-VF2.xml, testfx_output.tar.gz

Build information and commands

GIT: c2bce30724f34ac65c8d4018925108b3c2c1ae8f
CI: a8426a46d8575dfcb3b5fec0d7d0b7a7c118d690
REPO: tomeksowi/runtime
BRANCH: hw-intrinsics
CONFIG: Release
LIB_CONFIG: Release

RISC-V Release-CLR-QEMU: 9527 / 9547 (99.79%)
=======================
      passed: 9527
      failed: 3
     skipped: 106
      killed: 17
------------------------
  TOTAL libs: 9653
 TOTAL tests: 9653
   REAL time: 2h 47min 40s 52ms
=======================

Release-CLR-QEMU.md, Release-CLR-QEMU.xml, testclr_output.tar.gz

Build information and commands

GIT: c2bce30724f34ac65c8d4018925108b3c2c1ae8f
CI: a8426a46d8575dfcb3b5fec0d7d0b7a7c118d690
REPO: tomeksowi/runtime
BRANCH: hw-intrinsics
CONFIG: Release
LIB_CONFIG: Release

RISC-V Release-FX-QEMU: 632088 / 656489 (96.28%)
=======================
      passed: 632088
      failed: 511
     skipped: 1403
      killed: 23890
------------------------
  TOTAL libs: 258
 TOTAL tests: 657892
   REAL time: 1h 55min 8s 138ms
=======================

Release-FX-QEMU.md, Release-FX-QEMU.xml, testfx_output.tar.gz

Build information and commands

GIT: c2bce30724f34ac65c8d4018925108b3c2c1ae8f
CI: a8426a46d8575dfcb3b5fec0d7d0b7a7c118d690
REPO: tomeksowi/runtime
BRANCH: hw-intrinsics
CONFIG: Release
LIB_CONFIG: Release

@clamp03 clamp03 added the arch-riscv Related to the RISC-V architecture label Mar 27, 2025
@@ -34,6 +34,19 @@ static const HWIntrinsicInfo hwIntrinsicInfoArray[] = {
/* category */ category \
},
#include "hwintrinsiclistarm64.h"
#elif defined (TARGET_RISCV64)
#define HARDWARE_INTRINSIC(isa, name, size, numarg, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, category, flag) \
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

nit: maybe better to define this macro once under #if defined(TARGET_XARCH) || defined (TARGET_ARM64) || defined (TARGET_RISCV64).

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
arch-riscv Related to the RISC-V architecture area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI community-contribution Indicates that the PR has been added by a community member
Projects
None yet
Development

Successfully merging this pull request may close these issues.

4 participants