Improving VitisBuild

[bwintermann]

A lot of changes are necessary to make Multi-FPGA possible happen in VitisBuild. Since the aim is to improve this transformation in general, I'll make these changes on a separate branch so that we can all benefit from it before Multi-FPGA is fully merged.

Currently VitisBuild is a collection of string-concatinations that make certain assumptions of what the dataflow graph looks like. This very much made sense at the time because, as is officially mentioned as well, you usually want to integrate the stitched IP into your own custom design, so this step is not required for many users. However, to make it a viable tool for any user we want to be able to input an ONNX file and get a bitstream out of it. Both for Multi-FPGA and generally more complex dataflow graphs (for example multiple output heads etc.) this current flow won't work.

To fix this, I'll implement a new VitisBuild flow. One class keeps track of the configuration for a design. It can be used via it's method and avoids tedious string concatenation for it's user. The VitisLink transformation itself will be changed too. You start with an empty configuration and add components that are automatically connected via AXI streams. You pass what component you want to add, it will add it and return the new endpoint to attach new components to. This also has the benefit that measurement kernels, network communication kernels, etc. can all be included easily afterwards, without changing the entire build flow.