Add DDR3 PHY for Lattice Nexus FPGAs - #396
Merged
Merged
Conversation
Signed-off-by: gatecat <gatecat@ds0.me>
Contributor
Author
|
... and with YosysHQ/nextpnr@c2cbdc7 the nextpnr support should be in place (edge clock routing might not be 100% reliable but I'll fix that soon too) |
Align related declarations and the DQSBUF/DELAYB primitive argument tables with the LiteX coding style. This is a formatting-only change with no functional impact.
Owner
|
Awesome, thanks @gatecat! This this is a first good step that we can merge (I just applied cosmetic alignments to it). I'll try to suggest a follow up PR for the cleanup/latency improvement to have a proper solution. |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Tested with Radiant 2025.2 on the Certus-NX Versa board (litex-hub/litex-boards#757), nextpnr support hopefully coming very soon too.
This is mostly cribbed from the ECP5 PHY with changes to latencies where necessary. The part I'm least sure about is the half-system-clock (i.e. 1 memory clock) latency difference for writes. Currently this is dealt with by adding one to CWL but I'm not sure if a write bitslip on DQ/DQS (like 7-series) is overall a more robust solution to this.
In the future this could also be extended to support 8:1 mode as the Nexus devices have