phy: Align Artix-7 DDR3 reads without altering CL

[enjoy-digital]

Follow-up to #397 and @gatecat's observation about the similar Artix-7 read-path workaround.

Summary

• Keep the frequency-selected DDR3 CL unchanged in MR0.
• Move the Artix-7 read command by one memory-clock phase to retain the established ISERDESE2 word alignment.
• Fold DFI phase wrapping into the controller-visible read latency.
• Add Series-7 settings and MR0 tests covering default frequencies, every legal DDR3 CL, command latencies, and the unchanged Kintex-7 path.

Rationale

Since 6f323f6, the Artix-7 PHY has calculated its read phase and system latency from the selected CL but programmed CL + 1 in MR0. This places returned data one memory-clock phase into the ISERDESE2 word and improved read-leveling reliability, but it represents PHY alignment by changing the DRAM timing configuration. It also turns an explicitly selected CL 14 into the unsupported MR0 value 15.

The new schedule keeps the same intra-word read position by incrementing rdphase instead. divmod() normalizes the phase and carries a phase wrap into read_latency, making both parts of the timing relationship explicit.

Testing

• pytest -q test/test_s7ddrphy.py test/test_ddr3_phy_settings.py test/test_nxddrphy.py test/test_init.py test/test_gen.py: 13 passed, 86 subtests passed.
• Artix-7 PHY standalone Verilog elaboration: 2,628 lines generated with the expected OSERDESE2/ISERDESE2 instances.
• Digilent Arty SoC generation with gateware/software compilation disabled: completed successfully; generated settings are CL 6, CWL 5, read phase 3, and write phase 3 at 100 MHz.

Hardware Validation

This is intentionally a draft until it has been exercised on Artix-7 hardware. The useful checks are read-leveling windows and repeated memory tests at 50, 75, 100, and 125 MHz. A phase-wrap configuration, such as CL 13, should also be tested if practical because it reduces the controller-visible read latency by one system cycle.

[enjoy-digital]

Validated 624444c on an Arty A7-35 with LiteX 93c8d230, LiteX-Boards
2f06d08a, and Vivado 2025.2.

Build results:

• Default Arty design at 100MHz, with DDR3 at 800MT/s.
• Synthesis, placement, routing, DRC, and bitstream generation completed successfully.
• Timing met with setup WNS +0.571ns and hold WHS +0.017ns, with no failing endpoints.

Hardware results:

• Loaded the bitstream into an Arty A7-35 over JTAG.
• The BIOS reports CL-6 CWL-5, confirming that MR0 keeps the selected DDR3 CL instead of using the previous CL+1 workaround.
• Read leveling found stable windows on both byte lanes (18+-6 and 18+-5 taps).
• The automatic 2MiB memory test completed with Memtest OK.
• An additional 8MiB sdram_test completed with Memtest OK.

This confirms the adjusted read schedule works on Artix-7 hardware while preserving the frequency-selected DDR3 CL. CI is also green, so I am going to merge this.