How to pass defines to verilator/yosys #2283
Description
I have verilog code that is included into a litex project and I want to be able to
use this code in both simulation and for synthesis.
This is currently not that easy to do. for example in the simulation I added a $finish() statment
that is not well understood by yosys. I therefore would like to be able to pass defines during simulation and/or during
synthesis to be able to use the same code during simulation and sysnthesis.
For similar resaons I would like to be able to invoke the verilated code with plusargs (to tweak the simulation at runtime)
and be able to pass additional argument to verilator during compilation like -Wno-CASEINCOMPLETE
https://github.com/enjoy-digital/litex/blob/master/litex/build/sim/core/Makefile#L44
What would be a good approach?