Search results

Platforms/targets with two ETH

Status: Open.

#2416 In enjoy-digital/litex;

· ermachkov opened on Feb 11, 2026

How should the bus configuration in the vexii litex integration be handled?

Status: Open.

#2401 In enjoy-digital/litex;

· cklarhorst opened on Jan 13, 2026

Can't extract CSR name from code in Python 3.14

Status: Open.

#2399 In enjoy-digital/litex;

· david-sawatzke opened on Jan 13, 2026

litex_bare_metal_demo not starting on VexiiRiscv@Nexys4

Status: Open.

#2392 In enjoy-digital/litex;

· KunoTV opened on Jan 7, 2026

M-Labs is leaving GitHub

Status: Open.

#2388 In enjoy-digital/litex;

· sbourdeauducq opened on Jan 3, 2026

support cocotb+verilator for sim

Status: Open.

#2380 In enjoy-digital/litex;

· DavisLiu1989 opened on Dec 5, 2025

float C computing on VexRiscV and global custom_app process

Status: Open.

#2378 In enjoy-digital/litex;

· PJfixer opened on Dec 3, 2025

SoC : add AXI master output

question

Status: Open.

#2377 In enjoy-digital/litex;

· PJfixer opened on Dec 2, 2025

Using LiteScope with the PCIe on a LiteX Acorn Baseboard Mini

question

Status: Open.

#2372 In enjoy-digital/litex;

· Skinbow opened on Nov 24, 2025

Litex build flow for Zynq-7020 device using Vivado 2024.2 stuck after synthesis

bug?

question

Status: Open.

#2369 In enjoy-digital/litex;

· gkirilow-motec opened on Nov 18, 2025

drop support for --csr-data-width=8

enhancement

question

Status: Open.

#2368 In enjoy-digital/litex;

· maass-hamburg opened on Nov 18, 2025

Solved linker.ld issue causing unaligned access

Status: Open.

#2366 In enjoy-digital/litex;

· pratipm opened on Nov 12, 2025